ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite
With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to...
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| Vydáno v: | 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) s. 349 - 350 |
|---|---|
| Hlavní autor: | |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
New York, NY, USA
ACM
05.11.2012
IEEE |
| Edice: | ACM Conferences |
| Témata: | |
| ISBN: | 9781450315739, 1450315739 |
| ISSN: | 1092-3152 |
| On-line přístup: | Získat plný text |
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| Abstract | With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most accurate prediction possible their runtime prohibits an adoption at all levels of the design flow. Alternative traditional rule checking including pattern matching techniques are fast but have a limited application in finding locations that were not part the training set. Several approaches to improve the accuracy of the prediction to reduce the number of miss structures and false detections have been proposed, but none have yielded and acceptable tradeoff between accuracy and runtime. This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates. |
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| AbstractList | With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most accurate prediction possible their runtime prohibits an adoption at all levels of the design flow. Alternative traditional rule checking including pattern matching techniques are fast but have a limited application in finding locations that were not part the training set. Several approaches to improve the accuracy of the prediction to reduce the number of miss structures and false detections have been proposed, but none have yielded and acceptable tradeoff between accuracy and runtime. This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates. |
| Author | Torres, J. Andres |
| Author_xml | – sequence: 1 givenname: J. Andres surname: Torres fullname: Torres, J. Andres organization: Mentor Graphics Corporation, Wilsonville, OR |
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| Keywords | classification algorithms computational geometry fuzzy sets circuits data systems nanoscale devices |
| Language | English |
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| SubjectTerms | Accuracy Applied computing -- Arts and humanities -- Architecture (buildings) -- Computer-aided design Applied computing -- Physical sciences and engineering -- Engineering -- Computer-aided design circuits Classification algorithms Computational geometry Computing methodologies -- Artificial intelligence -- Knowledge representation and reasoning -- Probabilistic reasoning Computing methodologies -- Artificial intelligence -- Knowledge representation and reasoning -- Vagueness and fuzzy logic Data systems Design automation fuzzy sets Hardware -- Hardware validation -- Functional verification Integrated circuit modeling Layout nanoscale devices Pattern matching Solid modeling |
| Title | ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite |
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