Student research poster: A low complexity cache sharing mechanism to address system fairness

Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the...

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Vydáno v:2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) s. 455
Hlavní autoři: Selfa, Vicent, Sahuquillo, Julio, Petit, Salvador, Gomez, Maria E.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: ACM 01.09.2016
Témata:
Binary trees
Complexity theory
Computers
Distance measurement
Performance evaluation
Program processors
Runtime
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Abstract Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the performance of individual applications compared to isolated execution. The difference between the progresses of the running applications yields the system to unpredictable behavior and causes a fairness problem. This problem can be addressed by carefully partitioning cache resources among the contending applications, but to be effective, a partitioning approach needs to estimate the per-application progress.
AbstractList Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these systems, requests from multiple applications compete for the cache resources, degrading to different extents their progress, quantified as the performance of individual applications compared to isolated execution. The difference between the progresses of the running applications yields the system to unpredictable behavior and causes a fairness problem. This problem can be addressed by carefully partitioning cache resources among the contending applications, but to be effective, a partitioning approach needs to estimate the per-application progress.
Author Gomez, Maria E.
Selfa, Vicent
Petit, Salvador
Sahuquillo, Julio
Author_xml – sequence: 1
  givenname: Vicent
  surname: Selfa
  fullname: Selfa, Vicent
  email: viselol@disca.upv.es
  organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain
– sequence: 2
  givenname: Julio
  surname: Sahuquillo
  fullname: Sahuquillo, Julio
  organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain
– sequence: 3
  givenname: Salvador
  surname: Petit
  fullname: Petit, Salvador
  organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain
– sequence: 4
  givenname: Maria E.
  surname: Gomez
  fullname: Gomez, Maria E.
  organization: Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain
BookMark eNotj01LxDAYhCPoQdc9e_CSP9A1X82Ht2VRV1jwoN6EJU3e2ECblqSi--8N6GkYhmeYuULnaUqA0A0lG0pFe8eMVIbrDTOKCinO0NooXQPCBWXUXKKP1-XLQ1pwhgI2ux7PU1kg3-MtHqZv7KZxHuAnLifsrOsBl97mmD7xCK63KZYRLxO23le-4HKq7IiDjTlVf40ugh0KrP91hd4fH952--bw8vS82x4ay4RaGi06rYNoA5FEBhs6FWgbhDAavPK-VU47K5mGurkj3BEhaZC0c4F7p4nhK3T71xsB4DjnONp8OirV1vOM_wJXH1ER
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1145/2967938.2971464
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781450341219
1450341217
EndPage 455
ExternalDocumentID 7756792
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-a247t-84b88f45f0606fafb7f15f4498ed7dd57c8ca628e412b03c0461f61bcf3dc8093
IEDL.DBID RIE
ISICitedReferencesCount 0
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000392249100052&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Thu Jun 29 18:38:04 EDT 2023
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a247t-84b88f45f0606fafb7f15f4498ed7dd57c8ca628e412b03c0461f61bcf3dc8093
PageCount 1
ParticipantIDs ieee_primary_7756792
PublicationCentury 2000
PublicationDate 2016-Sept.
PublicationDateYYYYMMDD 2016-09-01
PublicationDate_xml – month: 09
  year: 2016
  text: 2016-Sept.
PublicationDecade 2010
PublicationTitle 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT)
PublicationTitleAbbrev PACT
PublicationYear 2016
Publisher ACM
Publisher_xml – name: ACM
Score 1.9614575
Snippet Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these...
SourceID ieee
SourceType Publisher
StartPage 455
SubjectTerms Binary trees
Complexity theory
Computers
Distance measurement
Performance evaluation
Program processors
Runtime
Title Student research poster: A low complexity cache sharing mechanism to address system fairness
URI https://ieeexplore.ieee.org/document/7756792
WOSCitedRecordID wos000392249100052&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA61ePCk0opvcvDotrt5x5uIxYOUgg96EEqSndCC7ZZ2q_58k92lInjxFhJCYMLMZDLzfYPQlUsd8dpBUKTYwkzkMjGU8cRSGfyr4UZUxPOvj3I4VOOxHrXQ9RYLAwBV8Rn04rDK5eeF28Svsr4M-6UOBndHSlFjtRq2nozxPtFhkaoe0TKoP_vVLqXyFoP9_51zgLo_sDs82jqUQ9SCRQe9PdXsk7ih5ZniZcRlrG7wLX4vPnFVEw5f4TGNXSRnxuupiX91eA4R1Dtbz3FZ4GBfYlyNa-JmHLM40cZ10cvg_vnuIWlaIiSGMFkmilmlPOM-DYGHN95Kn3HPmFaQyzzn0ilnBFHAMmJT6iKduheZdZ7mTqWaHqH2oljAMcJOGK1CMAOGM2aAWZbZTIWrEzQFAeQEdaJkJsua9WLSCOX07-kztBeeEqKuvjpH7XK1gQu06z7K2Xp1WV3VN_7vmKA
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA6lCnpSacW3OXh0290km4c3EUvFWgpW6UEo2eyEFmy3tFv155vsLhXBi7eQEAITMq_M9w1CVyY0xCoD7iH5FmY8FYGmLA4SKpx91bHmBfH8a0_0-3I0UoMaut5gYQCgKD6Dlh8Wf_lpZtY-VdYWbr9QTuFu-c5ZFVqr4uuJWNwmyi1T2SJKOAXAfjVMKexFZ-9_J-2j5g_wDg82JuUA1WDeQG_PJf8kroh5JnjhkRnLG3yL37NPXFSFw5dzp7Hx9Mx4NdE-W4dn4GG909UM5xl2GsZH1rikbsb-H8druSZ66dwP77pB1RQh0ISJPJAskdKy2IYu9LDaJsJGsWVMSUhFmsbCSKM5kcAikoTUeEJ1y6PEWJoaGSp6iOrzbA5HCBuulXThDGgnTg0sYVESSXd5nIbAgRyjhpfMeFHyXowroZz8PX2JdrrDp96499B_PEW7zrHgZS3WGarnyzWco23zkU9Xy4vi2r4BHtyb6Q
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2016+International+Conference+on+Parallel+Architecture+and+Compilation+Techniques+%28PACT%29&rft.atitle=Student+research+poster%3A+A+low+complexity+cache+sharing+mechanism+to+address+system+fairness&rft.au=Selfa%2C+Vicent&rft.au=Sahuquillo%2C+Julio&rft.au=Petit%2C+Salvador&rft.au=Gomez%2C+Maria+E.&rft.date=2016-09-01&rft.pub=ACM&rft.spage=455&rft.epage=455&rft_id=info:doi/10.1145%2F2967938.2971464&rft.externalDocID=7756792