IMP: Indirect memory prefetcher

Machine learning, graph analytics and sparse linear algebra-based applications are dominated by irregular memory accesses resulting from following edges in a graph or non-zero elements in a sparse matrix. These accesses have little temporal or spatial locality, and thus incur long memory stalls and...

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Veröffentlicht in:2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) S. 178 - 190
Hauptverfasser: Xiangyao Yu, Hughes, Christopher J., Satish, Nadathur, Devadas, Srinivas
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: ACM 01.12.2015
Schlagworte:
Arrays
Bandwidth
Hardware
Indexes
Multicore processing
Prefetching
Sparse matrices
ISSN:2379-3155
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Abstract Machine learning, graph analytics and sparse linear algebra-based applications are dominated by irregular memory accesses resulting from following edges in a graph or non-zero elements in a sparse matrix. These accesses have little temporal or spatial locality, and thus incur long memory stalls and large bandwidth requirements. A traditional streaming or striding prefetcher cannot capture these irregular access patterns. A majority of these irregular accesses come from indirect patterns of the form A[B[j]]. We propose an efficient hardware indirect memory prefetcher (IMP) to capture this access pattern and hide latency. We also propose a partial cacheline accessing mechanism for these prefetches to reduce the network and DRAM bandwidth pressure from the lack of spatial locality. Evaluated on 7 applications, IMP shows 56% speedup on average (up to 2.3×) compared to a baseline 64 core system with streaming prefetchers. This is within 23% of an idealized system. With partial cacheline accessing, we see another 9.4% speedup on average (up to 46.6%).
AbstractList Machine learning, graph analytics and sparse linear algebra-based applications are dominated by irregular memory accesses resulting from following edges in a graph or non-zero elements in a sparse matrix. These accesses have little temporal or spatial locality, and thus incur long memory stalls and large bandwidth requirements. A traditional streaming or striding prefetcher cannot capture these irregular access patterns. A majority of these irregular accesses come from indirect patterns of the form A[B[j]]. We propose an efficient hardware indirect memory prefetcher (IMP) to capture this access pattern and hide latency. We also propose a partial cacheline accessing mechanism for these prefetches to reduce the network and DRAM bandwidth pressure from the lack of spatial locality. Evaluated on 7 applications, IMP shows 56% speedup on average (up to 2.3×) compared to a baseline 64 core system with streaming prefetchers. This is within 23% of an idealized system. With partial cacheline accessing, we see another 9.4% speedup on average (up to 46.6%).
Author Hughes, Christopher J.
Xiangyao Yu
Satish, Nadathur
Devadas, Srinivas
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  surname: Xiangyao Yu
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  organization: Massachusetts Inst. of Technol., Cambridge, MA, USA
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  givenname: Christopher J.
  surname: Hughes
  fullname: Hughes, Christopher J.
  email: christopher.j.hughes@intel.com
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  givenname: Nadathur
  surname: Satish
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  email: nadathur.rajagopalan.satish@intel.com
  organization: Parallel Comput. Lab., Intel Labs., Santa Clara, CA, USA
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  givenname: Srinivas
  surname: Devadas
  fullname: Devadas, Srinivas
  email: devadas@mit.edu
  organization: Massachusetts Inst. of Technol., Cambridge, MA, USA
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Snippet Machine learning, graph analytics and sparse linear algebra-based applications are dominated by irregular memory accesses resulting from following edges in a...
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StartPage 178
SubjectTerms Arrays
Bandwidth
Hardware
Indexes
Multicore processing
Prefetching
Sparse matrices
Title IMP: Indirect memory prefetcher
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