A Multithreaded Initial Detailed Routing Algorithm Considering Global Routing Guides

Detailed routing is the most complicated and time-consuming stage in VLSI design and has become a critical process for advanced node enablement. To handle the high complexity of modern detailed routing, initial detailed routing is often employed to minimize design-rule violations to facilitate final...

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Vydané v:2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) s. 1 - 7
Hlavní autori: Sun, Fan-Keng, Chen, Hao, Chen, Ching-Yu, Hsu, Chen-Hao, Chang, Yao-Wen
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: ACM 01.11.2018
Predmet:
Advance Technologies
Complexity theory
Detailed Routing
Lead
Multithread
Physical Design
Pins
Routing
Timing
Wires
ISSN:1558-2434
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Shrnutí:Detailed routing is the most complicated and time-consuming stage in VLSI design and has become a critical process for advanced node enablement. To handle the high complexity of modern detailed routing, initial detailed routing is often employed to minimize design-rule violations to facilitate final detailed routing, even though it is still not violation-free after initial routing. This paper presents a novel initial detailed routing algorithm to consider industrial design-rule constraints and optimize the total wirelength and via count. Our algorithm consists of three major stages: (1) an effective pin-access point generation method to identify valid points to model a complex pin shape, (2) a via-aware track assignment method to minimize the overlaps between assigned wire segments, and (3) a detailed routing algorithm with a novel negotiation-based rip-up and re-route scheme that enables multithreading and honors global routing information while minimizing design-rule violations. Experimental results show that our router outperforms all the winning teams of the 2018 ACM ISPD Initial Detailed Routing Contest, where the top-3 routers result in 23%, 52%, and 1224% higher costs than ours.
ISSN:1558-2434
DOI:10.1145/3240765.3240777