Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Negative bias temperature instability (NBTI) adversely affects the reliability of a processor by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across functional units and instructions: some are affected more (hence less reliable) than oth...

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Bibliographic Details
Published in:2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Rahimi, Abbas, Benini, Luca, Gupta, Rajesh K.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 29.05.2013
IEEE
Series:ACM Conferences
Subjects:
Adaptive Kernel
Aging
Aging-aware Compilation
Computer architecture
Computer systems organization > Architectures > Parallel architectures > Very long instruction word
Computer systems organization > Architectures > Serial architectures > Complex instruction set computing
Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing
Computer systems organization > Dependable and fault-tolerant systems and networks
Degradation
Dynamic Binary Optimizer
General and reference > Cross-computing tools and techniques > Performance
GPGPU
Kernel
NBTI
Networks > Network performance evaluation
Sensors
Software and its engineering > Software notations and tools > Compilers
Stress
VLIW
aging-aware compilation
dynamic binary optimizer
VLIW
NBTI
GPGPU
adaptive kernel
ISBN:1450320716, 9781450320719
ISSN:0738-100X
Online Access:Get full text
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Summary:Negative bias temperature instability (NBTI) adversely affects the reliability of a processor by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across functional units and instructions: some are affected more (hence less reliable) than others. This paper proposes a NBTI-aware compiler-directed very long instruction word (VLIW) assignment scheme that uniformly distributes the stress of instructions with the aim of minimizing aging of GPGPU architecture without any performance penalty. The proposed solution is an entirely software technique based on static workload characterization and online execution with NBTI monitoring that equalizes the expected lifetime of each processing element by regenerating aging-aware healthy kernels that respond to the specific health state of GPGPU. We demonstrate our approach on AMD Evergreen architecture where iso-throughput executions of the healthy kernels reduce NBTI-induced voltage threshold shift up to 49% (11%) compared to naïve kernel executions, with (without) architectural support for power-gating. The kernel adaption flow takes average of 13 millisecond on a typical host machine thus making it suitable for practical implementation.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488754