RTLcheck verifying the memory consistency of RTL designs

Paramount to the viability of a parallel architecture is the correct implementation of its memory consistency model (MCM). Although tools exist for verifying consistency models at several design levels, a problematic verification gap exists between checking an abstract microarchitectural specificati...

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Bibliographic Details
Published in:	MICRO-50 : the 50th annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA pp. 463 - 476
Main Authors:	Manerkar, Yatin A., Lustig, Daniel, Martonosi, Margaret, Pellauer, Michael
Format:	Conference Proceeding
Language:	English
Published:	New York, NY, USA ACM 14.10.2017
Series:	ACM Conferences
Subjects:	automated verification Computer bugs Computer systems organization > Architectures > Parallel architectures Hardware Hardware > Hardware validation > Functional verification Hardware > Hardware validation > Functional verification > Assertion checking Hardware design languages Memory consistency models Microarchitecture Multicore processing Pipelines RTL SVA memory consistency models RTL automated verification SVA
ISBN:	1450349528, 9781450349529
ISSN:	2379-3155
Online Access:	Get full text
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