Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks

Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry blocks. Since hardened blocks can be configured in different ways, a variety of datapath patterns can be mapped into these block...

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Veröffentlicht in:	Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design S. 1 - 9
Hauptverfasser:	Ustun, Ecenur, Deng, Chenhui, Pal, Debjit, Li, Zhijing, Zhang, Zhiru
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	Association on Computer Machinery 02.11.2020
Schlagworte:	Adders arithmetic-intensive designs Computer architecture datapath patterns delay estimation DSP blocks field programmable gate arrays FPGA HLS GNN models graph neural networks graph theory high level synthesis inductive learning learning (artificial intelligence) modern heterogeneous FPGA architectures neural nets operation delay prediction operation mapping patterns Optimization resource usage Task analysis
ISSN:	1558-2434
Online-Zugang:	Volltext
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