Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks
Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry blocks. Since hardened blocks can be configured in different ways, a variety of datapath patterns can be mapped into these block...
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| Vydané v: | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 1 - 9 |
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Association on Computer Machinery
02.11.2020
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| ISSN: | 1558-2434 |
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| Abstract | Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry blocks. Since hardened blocks can be configured in different ways, a variety of datapath patterns can be mapped into these blocks. We observe that existing high-level synthesis (HLS) tools often fail to capture some of the operation mapping patterns, leading to limited estimation accuracy in terms of resource usage and delay. To address this deficiency, we propose to exploit graph neural networks (GNN) to automatically learn operation mapping patterns. We apply GNN models that are trained on microbenchmarks directly to realistic designs through inductive learning. Experimental results show that our approach can effectively infer various valid mapping patterns on both microbenchmarks and realistic designs. Furthermore, the proposed framework is exploited to improve the accuracy of delay estimation in HLS. |
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| AbstractList | Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP blocks and carry blocks. Since hardened blocks can be configured in different ways, a variety of datapath patterns can be mapped into these blocks. We observe that existing high-level synthesis (HLS) tools often fail to capture some of the operation mapping patterns, leading to limited estimation accuracy in terms of resource usage and delay. To address this deficiency, we propose to exploit graph neural networks (GNN) to automatically learn operation mapping patterns. We apply GNN models that are trained on microbenchmarks directly to realistic designs through inductive learning. Experimental results show that our approach can effectively infer various valid mapping patterns on both microbenchmarks and realistic designs. Furthermore, the proposed framework is exploited to improve the accuracy of delay estimation in HLS. |
| Author | Deng, Chenhui Ustun, Ecenur Li, Zhijing Zhang, Zhiru Pal, Debjit |
| Author_xml | – sequence: 1 givenname: Ecenur surname: Ustun fullname: Ustun, Ecenur email: eu49@cornell.edu organization: School of Electrical and Computer Engineering, Cornell University,Ithaca,NY – sequence: 2 givenname: Chenhui surname: Deng fullname: Deng, Chenhui email: cd574@cornell.edu organization: School of Electrical and Computer Engineering, Cornell University,Ithaca,NY – sequence: 3 givenname: Debjit surname: Pal fullname: Pal, Debjit email: debjit.pal@cornell.edu organization: School of Electrical and Computer Engineering, Cornell University,Ithaca,NY – sequence: 4 givenname: Zhijing surname: Li fullname: Li, Zhijing email: zl679@cornell.edu organization: School of Electrical and Computer Engineering, Cornell University,Ithaca,NY – sequence: 5 givenname: Zhiru surname: Zhang fullname: Zhang, Zhiru email: zhiruz@cornell.edu organization: School of Electrical and Computer Engineering, Cornell University,Ithaca,NY |
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| Snippet | Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP... |
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| SubjectTerms | Adders arithmetic-intensive designs Computer architecture datapath patterns delay estimation DSP blocks field programmable gate arrays FPGA HLS GNN models graph neural networks graph theory high level synthesis inductive learning learning (artificial intelligence) modern heterogeneous FPGA architectures neural nets operation delay prediction operation mapping patterns Optimization resource usage Task analysis |
| Title | Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks |
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