Hardware transactional memory for GPU architectures

Graphics processor units (GPUs) are designed to efficiently exploit thread level parallelism (TLP), multiplexing execution of 1000s of concurrent threads on a relatively smaller set of single-instruction, multiple-thread (SIMT) cores to hide various long latency operations. While threads within a CU...

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Bibliographische Detailangaben

Veröffentlicht in:	MICRO 44 : Proceedings of the 44th Annual IEEE/ACM Symposium on Microarchitecture, December 4 - 7, 2011 Porto Alegre, RS - Brazil S. 296 - 307
Hauptverfasser:	Fung, Wilson W. L., Singh, Inderpreet, Brownsword, Andrew, Aamodt, Tor M.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	ACM 01.12.2011
Schlagworte:	Computer architecture Design Graphics processing units Hardware Instruction sets Programming Synchronization System recovery
Online-Zugang:	Volltext
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