Rapid identification of architectural bottlenecks via precise event counting

On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performance counters, however, is limited by ineffic...

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Vydáno v:2011 38th Annual International Symposium on Computer Architecture (ISCA) s. 353 - 364
Hlavní autoři: Demme, John, Sethumadhavan, Simha
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 04.06.2011
IEEE
Edice:ACM Conferences
Témata:
Computer architecture
General and reference > Cross-computing tools and techniques > Measurement
General and reference > Cross-computing tools and techniques > Metrics
Hardware
Hardware > Hardware validation
Hardware Performance Counters
Instruments
Kernel
Libraries
Linux
Locking
Performance Evaluation
Radiation detectors
performance evaluation
hardware performance counters
locking
ISBN:9781450304726, 1450304729
ISSN:1063-6897
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Abstract On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performance counters, however, is limited by inefficient techniques used today to access them. Current access techniques rely on imprecise sampling or heavyweight kernel interaction forcing users to choose between precision or speed and thus restricting the use of performance counter hardware. In this paper, we describe new methods that enable precise, lightweight interfacing to on-chip performance counters. These low-overhead techniques allow precise reading of virtualized counters in low tens of nanoseconds, which is one to two orders of magnitude faster than current access techniques. Further, these tools provide several fresh insights on the behavior of modern parallel programs such as MySQL and Firefox, which were previously obscured (or impossible to obtain) by existing methods for characterization. Based on case studies with our new access methods, we discuss seven implications for computer architects in the cloud era and three methods for enhancing hardware counters further. Taken together, these observations have the potential to open up new avenues for architecture research.
AbstractList On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performance counters, however, is limited by inefficient techniques used today to access them. Current access techniques rely on imprecise sampling or heavyweight kernel interaction forcing users to choose between precision or speed and thus restricting the use of performance counter hardware. In this paper, we describe new methods that enable precise, lightweight interfacing to on-chip performance counters. These low-overhead techniques allow precise reading of virtualized counters in low tens of nanoseconds, which is one to two orders of magnitude faster than current access techniques. Further, these tools provide several fresh insights on the behavior of modern parallel programs such as MySQL and Firefox, which were previously obscured (or impossible to obtain) by existing methods for characterization. Based on case studies with our new access methods, we discuss seven implications for computer architects in the cloud era and three methods for enhancing hardware counters further. Taken together, these observations have the potential to open up new avenues for architecture research.
On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performance counters, however, is limited by inefficient techniques used today to access them. Current access techniques rely on imprecise sampling or heavyweight kernel interaction forcing users to choose between precision or speed and thus restricting the use of performance counter hardware. In this paper, we describe new methods that enable precise, lightweight interfacing to on-chip performance counters. These low-overhead techniques allow precise reading of virtualized counters in low tens of nanoseconds, which is one to two orders of magnitude faster than current access techniques. Further, these tools provide several fresh insights on the behavior of modern parallel programs such as MySQL and Firefox, which were previously obscured (or impossible to obtain) by existing methods for characterization. Based on case studies with our new access methods, we discuss seven implications for computer architects in the cloud era and three methods for enhancing hardware counters further. Taken together, these observations have the potential to open up new avenues for architecture research.
Author Demme, John
Sethumadhavan, Simha
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Keywords performance evaluation
hardware performance counters
locking
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Snippet On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors...
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SubjectTerms Computer architecture
General and reference -- Cross-computing tools and techniques -- Measurement
General and reference -- Cross-computing tools and techniques -- Metrics
Hardware
Hardware -- Hardware validation
Hardware Performance Counters
Instruments
Kernel
Libraries
Linux
Locking
Performance Evaluation
Radiation detectors
Title Rapid identification of architectural bottlenecks via precise event counting
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