FPGA in Rough-Granular Computing: Reduct Generation
In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to soft...
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| Published in: | 2014 IEEE/WIC/ACM International Joint Conferences on Web Intelligence (WI) and Intelligent Agent Technologies (IAT) Vol. 2; pp. 364 - 370 |
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| Main Authors: | , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
01.08.2014
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| Abstract | In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation. |
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| AbstractList | In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation. |
| Author | Stepaniuk, Jaroslaw Kopczynski, Maciej Grzes, Tomasz |
| Author_xml | – sequence: 1 givenname: Maciej surname: Kopczynski fullname: Kopczynski, Maciej email: m.kopczynski@pb.edu.pl organization: Fac. of Comput. Sci., Bialystok Univ. of Technol., Bialystok, Poland – sequence: 2 givenname: Tomasz surname: Grzes fullname: Grzes, Tomasz email: t.grzes@pb.edu.pl organization: Fac. of Comput. Sci., Bialystok Univ. of Technol., Bialystok, Poland – sequence: 3 givenname: Jaroslaw surname: Stepaniuk fullname: Stepaniuk, Jaroslaw email: j.stepaniuk@pb.edu.pl organization: Fac. of Comput. Sci., Bialystok Univ. of Technol., Bialystok, Poland |
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| PublicationTitle | 2014 IEEE/WIC/ACM International Joint Conferences on Web Intelligence (WI) and Intelligent Agent Technologies (IAT) |
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| Snippet | In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world... |
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| StartPage | 364 |
| SubjectTerms | Clocks Digital systems Field programmable gate arrays FPGA Hardware hardware solution Multiplexing Radiation detectors reduct rough set Software |
| Title | FPGA in Rough-Granular Computing: Reduct Generation |
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