FPGA in Rough-Granular Computing: Reduct Generation

In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to soft...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:2014 IEEE/WIC/ACM International Joint Conferences on Web Intelligence (WI) and Intelligent Agent Technologies (IAT) Ročník 2; s. 364 - 370
Hlavní autoři: Kopczynski, Maciej, Grzes, Tomasz, Stepaniuk, Jaroslaw
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.08.2014
Témata:
Clocks
Digital systems
Field programmable gate arrays
FPGA
Hardware
hardware solution
Multiplexing
Radiation detectors
reduct
rough set
Software
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation.
DOI:10.1109/WI-IAT.2014.120