Fast and accurate source-level simulation of software timing considering complex code optimizations

This paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components which is then integrated into a SystemC transact...

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Vydáno v:2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) s. 486 - 491
Hlavní autoři: Stattelmann, Stefan, Bringmann, Oliver, Rosenstiel, Wolfgang
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 05.06.2011
IEEE
Edice:ACM Conferences
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ISBN:1450306365, 9781450306362
ISSN:0738-100X
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Shrnutí:This paper presents an approach for accurately estimating the execution time of parallel software components in complex embedded systems. Timing annotations obtained from highly optimized binary code are added to the source code of software components which is then integrated into a SystemC transaction-level simulation. This approach allows a fast evaluation of software execution times while being as accurate as conventional instruction set simulators. By simulating binary-level control flow in parallel to the original functionality of the software, even compiler optimizations heavily modifying the structure of the generated code can be modeled accurately. Experimental results show that the presented method produces timing estimates within the same level of accuracy as an established commercial tool for cycle-accurate instruction set simulation while being at least 20 times faster.
ISBN:1450306365
9781450306362
ISSN:0738-100X
DOI:10.1145/2024724.2024838