Perceptron-Based Prefetch Filtering
Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two main metrics that are generally at odds with one another: coverage, the fraction of baseline cache misses which the prefetcher brings into th...
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| Vydáno v: | 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA) s. 1 - 13 |
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ACM
01.06.2019
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| ISSN: | 2575-713X |
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| Abstract | Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two main metrics that are generally at odds with one another: coverage, the fraction of baseline cache misses which the prefetcher brings into the cache; and accuracy, the fraction of prefetches which are ultimately used. An overly aggressive prefetcher may improve coverage at the cost of reduced accuracy. Thus, performance may be harmed by this over-aggressiveness because many resources are wasted, including cache capacity and bandwidth. An ideal prefetcher would have both high coverage and accuracy. In this paper, we introduce Perceptron-based Prefetch Filtering (PPF) as a way to increase the coverage of the prefetches generated by an underlying prefetcher without negatively impacting accuracy. PPF enables more aggressive tuning of the underlying prefetcher, leading to increased coverage by filtering out the growing numbers of inaccurate prefetches such an aggressive tuning implies. We also explore a range of features to use to train PPF's perceptron layer to identify inaccurate prefetches. PPF improves performance on a memory-intensive subset of the SPEC CPU 2017 benchmarks by 3.78% for a single-core configuration, and by 11.4% for a 4-core configuration, compared to the underlying prefetcher alone. |
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| AbstractList | Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two main metrics that are generally at odds with one another: coverage, the fraction of baseline cache misses which the prefetcher brings into the cache; and accuracy, the fraction of prefetches which are ultimately used. An overly aggressive prefetcher may improve coverage at the cost of reduced accuracy. Thus, performance may be harmed by this over-aggressiveness because many resources are wasted, including cache capacity and bandwidth. An ideal prefetcher would have both high coverage and accuracy. In this paper, we introduce Perceptron-based Prefetch Filtering (PPF) as a way to increase the coverage of the prefetches generated by an underlying prefetcher without negatively impacting accuracy. PPF enables more aggressive tuning of the underlying prefetcher, leading to increased coverage by filtering out the growing numbers of inaccurate prefetches such an aggressive tuning implies. We also explore a range of features to use to train PPF's perceptron layer to identify inaccurate prefetches. PPF improves performance on a memory-intensive subset of the SPEC CPU 2017 benchmarks by 3.78% for a single-core configuration, and by 11.4% for a 4-core configuration, compared to the underlying prefetcher alone. |
| Author | Gratz, Paul V. Teran, Elvira Pugsley, Seth Jimenez, Daniel A. Bhatia, Eshan Chacon, Gino |
| Author_xml | – sequence: 1 givenname: Eshan surname: Bhatia fullname: Bhatia, Eshan organization: Texas A&M University – sequence: 2 givenname: Gino surname: Chacon fullname: Chacon, Gino organization: Texas A&M University – sequence: 3 givenname: Seth surname: Pugsley fullname: Pugsley, Seth organization: Intel Labs – sequence: 4 givenname: Elvira surname: Teran fullname: Teran, Elvira organization: Texas A&M International University – sequence: 5 givenname: Paul V. surname: Gratz fullname: Gratz, Paul V. organization: Texas A&M University – sequence: 6 givenname: Daniel A. surname: Jimenez fullname: Jimenez, Daniel A. organization: Texas A&M University and Barcelona Supercomputing Center |
| BookMark | eNotjD1LA0EQQFdRMMarLWwC1hdnZj9mt9SQqBAwhYJd2L2b1ZN4CXvX-O8NaPWK93iX6qzf96LUNcIc0dg7rYGdhbnWRAR8oqrA_ihAO-eCOVUTsmxrRv1-oaph-AIA8ozHaKJuN1IaOYxl39cPcZB2timSZWw-Z6tuN0rp-o8rdZ7jbpDqn1P1tlq-Lp7q9cvj8-J-XUcyPNaIJOgiZmqAKTFnS9HFDIGTSDRtAASIxjNbi60BTKZNPnMWSTokPVU3f99ORLaH0n3H8rP1wYMGp38BLe9AdA |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1145/3307650.3322207 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISBN | 9781450366694 1450366694 |
| EISSN | 2575-713X |
| EndPage | 13 |
| ExternalDocumentID | 8980306 |
| Genre | orig-research |
| GroupedDBID | 23M 29F 29O 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR AAWTH ACGFS ADZIZ ALMA_UNASSIGNED_HOLDINGS APO BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP IPLJI M43 OCL RIE RIL RIO ZY4 |
| ID | FETCH-LOGICAL-a247t-112e16a1f2c072b77f52a6af097beea4d90100a4877551d401b4db8f7feeb39b3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 78 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000521059600001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 07:44:36 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a247t-112e16a1f2c072b77f52a6af097beea4d90100a4877551d401b4db8f7feeb39b3 |
| PageCount | 13 |
| ParticipantIDs | ieee_primary_8980306 |
| PublicationCentury | 2000 |
| PublicationDate | 2019-June |
| PublicationDateYYYYMMDD | 2019-06-01 |
| PublicationDate_xml | – month: 06 year: 2019 text: 2019-June |
| PublicationDecade | 2010 |
| PublicationTitle | 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA) |
| PublicationTitleAbbrev | ISCA |
| PublicationYear | 2019 |
| Publisher | ACM |
| Publisher_xml | – name: ACM |
| SSID | ssj0002871781 ssj0019956 |
| Score | 2.4507456 |
| Snippet | Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | Accuracy Benchmark testing Computer architecture Costs Engines Filters Hardware Measurement Prefetching Tuning |
| Title | Perceptron-Based Prefetch Filtering |
| URI | https://ieeexplore.ieee.org/document/8980306 |
| WOSCitedRecordID | wos000521059600001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ1LSwMxEMeHtnjw5KMV3yzo0bS7m2wmuSoWD1J6UOmtJN0J9LKV2vr5neyuFcGLtxAIJIQwv3_mBXCrjST0hRMZpV4olCicNEHoiAtKM6DX3RrennEyMbOZnXbgbpcLQ0R18BkN47D25ZerxTZ-lY2MNRFxu9BF1E2u1u4_JZJ_Xbem9SDEjM22lE-mihHLdmQYGcroWUh_91KpTcn44H-bOITBT05eMt1ZmyPoUHUMB99NGZL2jfbhZtqEqqxXlbhnE1XyKgrxcpLxMrrGefUAXsePLw9Pou2EIFyucCMYiijTLgv5IsXcI4Yid9qF1KIncqqMQRapY_GBTEAlayavSm8CBmKxbL08gV61qugUEgqs6EhaQ7pQLjBgOxksWhY2ZRkwPYN-PPP8vSl2MW-Pe_739AXsM0HYJnbqEnqb9ZauYG_xuVl-rK_rG_oCeaGOmg |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ1NSwMxEIaHWgU9VW3Fbxf0aNrsbnaTXBVLxVp6qNJbSZoJeNlKbf39TnbXiuDFWwgEEkKY5818AdzkKkVpM8Ni5JYJmUpmUuVZHnBB5AToZbeG16EcjdR0qscNuN3kwiBiGXyG3TAsffluMV-Hr7Ke0iog7hZsZ0IkvMrW2vyoBPYvK9fUPoSQs1kX84lF1iPhLglHumnwLfDf3VRKY9Jv_W8b-9D5ycqLxht7cwANLA6h9d2WIapfaRuux1WwynJRsDsyUo5WoQ_XE_XfgnOcVnfgpf8wuR-wuhcCM4mQK0ZYhHFuYp_MuUyslD5LTG4819IiGuFCmAU3JD8kMZAj1WSFs8pLjySXtU2PoFksCjyGCD1pOky1wjwTxhNim9RrqUnaOOclP4F2OPPsvSp3MauPe_r39BXsDibPw9nwcfR0BnvEE7qKpDqH5mq5xgvYmX-u3j6Wl-VtfQEZV5Hh |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2019+ACM%2FIEEE+46th+Annual+International+Symposium+on+Computer+Architecture+%28ISCA%29&rft.atitle=Perceptron-Based+Prefetch+Filtering&rft.au=Bhatia%2C+Eshan&rft.au=Chacon%2C+Gino&rft.au=Pugsley%2C+Seth&rft.au=Teran%2C+Elvira&rft.date=2019-06-01&rft.pub=ACM&rft.eissn=2575-713X&rft.spage=1&rft.epage=13&rft_id=info:doi/10.1145%2F3307650.3322207&rft.externalDocID=8980306 |