Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by u...

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Bibliographic Details
Published in:Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002 pp. 399 - 404
Main Authors: Badaroglu, Mustafa, Tiri, Kris, Donnay, StÉphane, Wambacq, Piet, Man, Hugo De, Verbauwhede, Ingrid, Gielen, Georges
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 10.06.2002
Series:ACM Conferences
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Hardware > Electronic design automation > High-level and register-transfer level synthesis > Datapath optimization
Hardware > Electronic design automation > Logic synthesis > Circuit optimization
Hardware > Hardware validation
Hardware > Hardware validation > Functional verification > Simulation and emulation
Hardware > Integrated circuits > Logic circuits > Sequential circuits
Hardware > Very large scale integration design
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
low-noise digital design
substrate noise
clock distribution networks
optimization
supply current shaping
di/dt noise
ISBN:1581134614, 9781581134612
ISSN:0738-100X
Online Access:Get full text
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Summary:In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by using statistical single cycle supply current profiles computed for every clock region taking the timing constraints into account. Our methodology is novel as it uses an error-driven compressed data set during the optimization over a number of clock regions specified for a significant reduction in substrate noise. It also produces a quality analysis of the computed latencies as a function of the clock skew. The experimental results show >x2 reduction of substrate noise generation from the circuits having four clock regions of which the latencies are optimized.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1581134614
9781581134612
ISSN:0738-100X
DOI:10.1145/513918.514021