Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming

In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits...

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Veröffentlicht in:	7th International Symposium on Quality Electronic Design (ISQED'06) S. 272 - 277
Hauptverfasser:	Fan, Jeffrey, Liao, I-Fan, Sheldon, X.-D, Cai, Yici, Hong, Xianlong
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	Washington, DC, USA IEEE Computer Society 27.03.2006 IEEE
Schriftenreihe:	ACM Conferences
Schlagworte:	Circuit noise Engines Hardware > Electronic design automation > Logic synthesis > Circuit optimization Hardware > Very large scale integration design Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors Linear programming Mathematics of computing > Mathematical analysis > Mathematical optimization > Continuous optimization > Linear programming Network-on-a-chip Noise reduction Optimization methods Partitioning algorithms Theory of computation > Design and analysis of algorithms > Mathematical optimization > Continuous optimization > Linear programming Time domain analysis Very large scale integration Voltage
ISBN:	9780769525235, 0769525237
ISSN:	1948-3287
Online-Zugang:	Volltext
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