Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming

In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:7th International Symposium on Quality Electronic Design (ISQED'06) s. 272 - 277
Hlavní autoři: Fan, Jeffrey, Liao, I-Fan, Sheldon, X.-D, Cai, Yici, Hong, Xianlong
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 27.03.2006
IEEE
Edice:ACM Conferences
Témata:
Circuit noise
Engines
Hardware > Electronic design automation > Logic synthesis > Circuit optimization
Hardware > Very large scale integration design
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
Linear programming
Mathematics of computing > Mathematical analysis > Mathematical optimization > Continuous optimization > Linear programming
Network-on-a-chip
Noise reduction
Optimization methods
Partitioning algorithms
Theory of computation > Design and analysis of algorithms > Mathematical optimization > Continuous optimization > Linear programming
Time domain analysis
Very large scale integration
Voltage
ISBN:9780769525235, 0769525237
ISSN:1948-3287
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits. We show that by directly optimizing the decap area as the objective function and using the time-domain adjoint method, SLP can deliver much better quality than existing methods based on the merged time-domain adjoint method. The partitioning strategy further improves the scalability of the proposed algorithm and makes it efficient for large circuits. The resulting algorithm is general enough for any P/G network. Experimental results demonstrate the advantage of the proposed method over existing state-of-the-art methods in terms of solution quality at a mild computation cost increase.
ISBN:9780769525235
0769525237
ISSN:1948-3287
DOI:10.1109/ISQED.2006.81