Achieving Out-of-Order Performance with Almost In-Order Complexity

There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identifie...

Full description

Saved in:
Bibliographic Details
Published in:2008 International Symposium on Computer Architecture pp. 3 - 12
Main Authors: Tseng, Francis, Patt, Yale N.
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.06.2008
IEEE
Series:ACM Conferences
Subjects:
Bars
Computer architecture
Hardware
Hardware > Electronic design automation > Methodologies for EDA
Hardware > Emerging technologies
Hardware > Hardware validation
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Hardware > Integrated circuits > Logic circuits > Design modules and hierarchy
Hardware > Very large scale integration design
Instruction sets
Microarchitecture
Out of order
Performance loss
Pipeline processing
Process design
Processor scheduling
ISBN:9780769531748, 0769531741
ISSN:1063-6897
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identified entity that enables the execution core to scale to wider widths by exploiting the small fanout and short lifetime of values produced by the program. Braid processing requires identification by the compiler, minor extensions to the ISA, and support by the microarchitecture. The result from processing braids is performance within 9% of a very aggressive conventional out-of-order microarchitecture with almost the complexity of an in-order implementation.
AbstractList There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identified entity that enables the execution core to scale to wider widths by exploiting the small fanout and short lifetime of values produced by the program. Braid processing requires identification by the compiler, minor extensions to the ISA, and support by the microarchitecture. The result from processing braids is performance within 9% of a very aggressive conventional out-of-order microarchitecture with almost the complexity of an in-order implementation.
Author Tseng, Francis
Patt, Yale N.
Author_xml – sequence: 1
  givenname: Francis
  surname: Tseng
  fullname: Tseng, Francis
– sequence: 2
  givenname: Yale N.
  surname: Patt
  fullname: Patt, Yale N.
BookMark eNqNkMtOwzAQRS1RJErpjh2bbFihFI_t2PEyRDwqVQoSsLYcZ0INTVI54dG_J1X7AaxmpHt0NXPOyaTtWiTkEugCgOrb5UueLRil6YLxEzLXKqVK6oSDEumETIFKHstUqzMy7_sPSiloqYDzKbnL3Nrjt2_fo-JriLs6LkKFIXrGUHehsa3D6McP6yjbNF0_RMv2CORds93grx92F-S0tpse58c5I28P96_5U7wqHpd5tootEzDENVKuhapK1GXiMJUllYoh6sqp8RxLtXRyXIVj2gHUiICi4lawSgJNLZ-Rq0OvR0SzDb6xYWdEkoyvwJheH1LrGlN23WdvgJq9HbO3Y_Z2DOMjd_MfzpTBY83_ADi2Y-4
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/ISCA.2008.23
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList

Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Computer Science
EndPage 12
ExternalDocumentID 4556711
Genre orig-research
GroupedDBID 6IE
6IF
6IG
6IH
6IK
6IL
6IM
6IN
AAJGR
AARBI
ACM
ADPZR
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
GUFHI
IERZE
OCL
RIB
RIC
RIE
RIL
RIO
23M
29F
29O
AAWTH
ACGFS
ADZIZ
CHZPO
IEGSK
IJVOP
IPLJI
M43
ZY4
ID FETCH-LOGICAL-a241t-fe03947dbe9b5ce86b0672ee9dc7196a096c6c714c29c11fee1e4d3a42d6108a3
IEDL.DBID RIE
ISBN 9780769531748
0769531741
ISICitedReferencesCount 18
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000257942700001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 1063-6897
IngestDate Wed Aug 27 02:15:37 EDT 2025
Wed Jan 31 06:44:29 EST 2024
Wed Jan 31 06:43:35 EST 2024
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MeetingName ISCA08: The 35th Annual International Symposium on Computer Architecture
MergedId FETCHMERGED-LOGICAL-a241t-fe03947dbe9b5ce86b0672ee9dc7196a096c6c714c29c11fee1e4d3a42d6108a3
PageCount 10
ParticipantIDs acm_books_10_1109_ISCA_2008_23
acm_books_10_1109_ISCA_2008_23_brief
ieee_primary_4556711
PublicationCentury 2000
PublicationDate 20080601
2008-June
PublicationDateYYYYMMDD 2008-06-01
PublicationDate_xml – month: 06
  year: 2008
  text: 20080601
  day: 01
PublicationDecade 2000
PublicationPlace Washington, DC, USA
PublicationPlace_xml – name: Washington, DC, USA
PublicationSeriesTitle ACM Conferences
PublicationTitle 2008 International Symposium on Computer Architecture
PublicationTitleAbbrev ISCA
PublicationYear 2008
Publisher IEEE Computer Society
IEEE
Publisher_xml – name: IEEE Computer Society
– name: IEEE
SSID ssj0001967133
ssj0019956
Score 1.8470801
Snippet There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not...
SourceID ieee
acm
SourceType Publisher
StartPage 3
SubjectTerms Bars
Computer architecture
Hardware
Hardware -- Electronic design automation -- Methodologies for EDA
Hardware -- Emerging technologies
Hardware -- Hardware validation
Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits
Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy
Hardware -- Very large scale integration design
Instruction sets
Microarchitecture
Out of order
Performance loss
Pipeline processing
Process design
Processor scheduling
Title Achieving Out-of-Order Performance with Almost In-Order Complexity
URI https://ieeexplore.ieee.org/document/4556711
WOSCitedRecordID wos000257942700001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LawIxEA5WeujJtlpqH5KDx6buI5vH0UqlQlGhD7wtm-wsFapbdC303zfJrkqhFHrLLmFZhoSZb2a--RDqGsihFRMe0UqGhGpPE-V7CQkCLxOMhzRwDO_XRz4ei9lMTmvoZseFAQDXfAa3dulq-WmuNzZV1qNRxLgl8h5wzkqu1j6fIhl3UiVVBcEyNl2lk4WECTv-z0J2aY6c8aHV5J3ts9h1xMve6GnQL1ssnYJRohc_dFec2xk2_vfDx6i15-_h6c4znaAaLE9RYyvggKv73ER3ff02B5tSwJNNQfKMTOwkTjzdswmwTdTi_vsiXxd4tKw22E_ZSZrFVwu9DO-fBw-kElUgiXHWBcnACyXlqQKpIg2CKVuMBZCp5saGiYE0mpkl1YHUvp8B-EDTMKFBaiItkYRnqL7Ml3COcAQGfrHI11yHNAIpM5WYACzjIjVhVgpt1DHmiy1aWMcObHgytvYttS-DsI26f2-I1WoOWRs1rWnjj3L-RlxZ9eL315foqOzpsJmSK1QvVhu4Rof6s5ivVx13aL4B8OS22A
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NS8NAEB1KFfRUtRXrR82hR9fmY7PJHmuxWKxtwSq9hWQzwYJNpE0F_727m7RFEMHbJiwhDLvMvJl58wDaEnKIiPkmERF3CBWmIJFlhsS2zcRnnkNtzfB-HXqjkT-b8UkFbrZcGETUzWd4q5a6lh9nYq1SZR3qusxTRN49l1LbLNhau4wKZ54WKylrCIqzqWudzCHMVwMAFWjn8tBJL1rO3tk8-9ueeN4ZPPe6RZOl1jAKxeKH8op2PP3a_375CBo7Bp8x2fqmY6hgegK1jYSDUd7oOtx1xdscVVLBGK9zkiVkrGZxGpMdn8BQqVqj-77IVrkxSMsN6lNqlmb-1YCX_v2090BKWQUSSnedkwRNh1MvjpBHrkCfRaoci8hj4UkbhhLUCCaXVNhcWFaCaCGNnZDasYy1_NA5hWqapXgGhosSgDHXEp5wqIucJ1EoQ7DE82MZaMXYhJY0X6DwwirQcMPkgbJvoX5pO01o_70hiJZzTJpQV6YNPooJHEFp1fPfX1_DwcP0aRgMB6PHCzgsOjxU3uQSqvlyjVewLz7z-WrZ0gfoG6mvuh8
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2008+International+Symposium+on+Computer+Architecture&rft.atitle=Achieving+Out-of-Order+Performance+with+Almost+In-Order+Complexity&rft.au=Tseng%2C+F.&rft.au=Patt%2C+Y.N.&rft.date=2008-06-01&rft.pub=IEEE&rft.isbn=9780769531748&rft.issn=1063-6897&rft.spage=3&rft.epage=12&rft_id=info:doi/10.1109%2FISCA.2008.23&rft.externalDocID=4556711
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1063-6897&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1063-6897&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1063-6897&client=summon