Achieving Out-of-Order Performance with Almost In-Order Complexity

There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identifie...

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Vydáno v:2008 International Symposium on Computer Architecture s. 3 - 12
Hlavní autoři: Tseng, Francis, Patt, Yale N.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 01.06.2008
IEEE
Edice:ACM Conferences
Témata:
Bars
Computer architecture
Hardware
Hardware > Electronic design automation > Methodologies for EDA
Hardware > Emerging technologies
Hardware > Hardware validation
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Hardware > Integrated circuits > Logic circuits > Design modules and hierarchy
Hardware > Very large scale integration design
Instruction sets
Microarchitecture
Out of order
Performance loss
Pipeline processing
Process design
Processor scheduling
ISBN:9780769531748, 0769531741
ISSN:1063-6897
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Shrnutí:There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identified entity that enables the execution core to scale to wider widths by exploiting the small fanout and short lifetime of values produced by the program. Braid processing requires identification by the compiler, minor extensions to the ISA, and support by the microarchitecture. The result from processing braids is performance within 9% of a very aggressive conventional out-of-order microarchitecture with almost the complexity of an in-order implementation.
ISBN:9780769531748
0769531741
ISSN:1063-6897
DOI:10.1109/ISCA.2008.23