Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory

We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be made strongly atomic by using memory protection on transactionally-held state, then showing how such a strongly-atomic STM c...

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Published in:2008 International Symposium on Computer Architecture pp. 115 - 126
Main Authors: Baugh, Lee, Neelakantam, Naveen, Zilles, Craig
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.06.2008
IEEE
Series:ACM Conferences
Subjects:
Abort Handler
Computer architecture
Computer science
Content management
Hardware
Hardware > Hardware validation
Hardware > Integrated circuits > Semiconductor memory
Hybrid
Memory Protection
Primitives
Proposals
Protection
Read-write memory
Software performance
Software safety
Software systems
Strong Atomicity
Theory of computation > Models of computation > Concurrency
Theory of computation > Models of computation > Concurrency > Parallel computing models
Transactional Memory
Hybrid
Transactional Memory
Primitives
Abort Handler
Memory Protection
Strong Atomicity
ISBN:9780769531748, 0769531741
ISSN:1063-6897
Online Access:Get full text
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Abstract We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be made strongly atomic by using memory protection on transactionally-held state, then showing how such a strongly-atomic STM can be used with a bounded hardware TM system to build a hybrid TM system in which zero-overhead hardware transactions may safely run concurrently with potentially-conflicting software transactions. We experimentally demonstrate how this hybrid TM organization avoids the common-case overheads associated with previous hybrid TM proposals, achieving performance rivaling an unbounded HTM system without the hardware complexity of ensuring completion of arbitrary transactions in hardware. As part of our findings, we identify key policies regarding contention management within and across the hardware and software TM components that are key to achieving robust performance with a hybrid TM.
AbstractList We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be made strongly atomic by using memory protection on transactionally-held state, then showing how such a strongly-atomic STM can be used with a bounded hardware TM system to build a hybrid TM system in which zero-overhead hardware transactions may safely run concurrently with potentially-conflicting software transactions. We experimentally demonstrate how this hybrid TM organization avoids the common-case overheads associated with previous hybrid TM proposals, achieving performance rivaling an unbounded HTM system without the hardware complexity of ensuring completion of arbitrary transactions in hardware. As part of our findings, we identify key policies regarding contention management within and across the hardware and software TM components that are key to achieving robust performance with a hybrid TM.
Author Neelakantam, Naveen
Baugh, Lee
Zilles, Craig
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Keywords Hybrid
Transactional Memory
Primitives
Abort Handler
Memory Protection
Strong Atomicity
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Snippet We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory...
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StartPage 115
SubjectTerms Abort Handler
Computer architecture
Computer science
Content management
Hardware
Hardware -- Hardware validation
Hardware -- Integrated circuits -- Semiconductor memory
Hybrid
Memory Protection
Primitives
Proposals
Protection
Read-write memory
Software performance
Software safety
Software systems
Strong Atomicity
Theory of computation -- Models of computation -- Concurrency
Theory of computation -- Models of computation -- Concurrency -- Parallel computing models
Transactional Memory
Title Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
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