Out-of-order parallel simulation for ESL design

At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottl...

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Veröffentlicht in:Proceedings of the Conference on Design, Automation and Test in Europe S. 141 - 146
Hauptverfasser: Chen, Weiwei, Han, Xu, Dömer, Rainer
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: San Jose, CA, USA EDA Consortium 12.03.2012
Schriftenreihe:ACM Conferences
Schlagworte:
Computer systems organization > Architectures > Parallel architectures
Computing methodologies > Modeling and simulation > Simulation evaluation
Hardware > Hardware validation > Functional verification > Simulation and emulation
ISBN:3981080181, 9783981080186
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits of parallel simulation. This paper presents a new out-of-order simulator for multi-core parallel DE simulation of hardware/software designs at any abstraction level. By localizing the simulation time and carefully handling events at different times, a system model can be simulated following a partial order of time. Subject to automatic static data analysis at compile time and table-based decisions at run time, threads can be issued early which reduces the idle time of available cores. Our experiments show high performance gains in simulation speed with only a small increase of compile time.
ISBN:3981080181
9783981080186
DOI:10.5555/2492708.2492743