Out-of-order parallel simulation for ESL design

At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottl...

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Bibliographic Details
Published in:Proceedings of the Conference on Design, Automation and Test in Europe pp. 141 - 146
Main Authors: Chen, Weiwei, Han, Xu, Dömer, Rainer
Format: Conference Proceeding
Language:English
Published: San Jose, CA, USA EDA Consortium 12.03.2012
Series:ACM Conferences
Subjects:
Computer systems organization > Architectures > Parallel architectures
Computing methodologies > Modeling and simulation > Simulation evaluation
Hardware > Hardware validation > Functional verification > Simulation and emulation
ISBN:3981080181, 9783981080186
Online Access:Get full text
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