Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabri...
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| Vydáno v: | Proceedings of the Conference on Design, Automation and Test in Europe s. 1591 - 1596 |
|---|---|
| Hlavní autoři: | , , |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
San Jose, CA, USA
EDA Consortium
12.03.2012
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| Edice: | ACM Conferences |
| Témata: | |
| ISBN: | 3981080181, 9783981080186 |
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| Abstract | This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with the high degree of variability in the process and environmental factors. Our framework is based on using on-chip delay sensors to improve timing prediction. Given a placed netlist at the pre-silicon stage, an optimization procedure is described which automatically generates the sensors subject to an area budget and available whitespace on the layout, in the presence of process variations. Each sensor is then generated as a sequence of logic gates with an approximate location on the layout at the pre-silicon stage. The on-chip sensor delay is then measured to predict the delays of individual design paths with less pessimism. In our experiments, we show that custom on-chip sensors can significantly increase the rate of predicting if a specified set of paths are failing their timing requirements. |
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| AbstractList | This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with the high degree of variability in the process and environmental factors. Our framework is based on using on-chip delay sensors to improve timing prediction. Given a placed netlist at the pre-silicon stage, an optimization procedure is described which automatically generates the sensors subject to an area budget and available whitespace on the layout, in the presence of process variations. Each sensor is then generated as a sequence of logic gates with an approximate location on the layout at the pre-silicon stage. The on-chip sensor delay is then measured to predict the delays of individual design paths with less pessimism. In our experiments, we show that custom on-chip sensors can significantly increase the rate of predicting if a specified set of paths are failing their timing requirements. |
| Author | Davoodi, Azadeh Li, Min Xie, Lin |
| Author_xml | – sequence: 1 givenname: Min surname: Li fullname: Li, Min organization: University of Wisconsin at Madison, WI – sequence: 2 givenname: Azadeh surname: Davoodi fullname: Davoodi, Azadeh email: adavoodi@wisc.edu organization: University of Wisconsin at Madison, WI – sequence: 3 givenname: Lin surname: Xie fullname: Xie, Lin organization: Cadence Design Systems, San Jose, CA |
| BookMark | eNqNkE9PxCAQxUnURHfds1eOXrpCKYEeTeO_ZBMveiZTChbtQtNBP7-o_QDO5b1M5jd5eRtyGlN0hFxxtpdlbuqmrRXT-6KCtfKEbESrOdOMa35OdojvjDHOVaNbfUGG7hNzOtIUKzuGmaKLmBakPi10TpgrDFOwKVIPxcQ3OkMeacA0QQ5lHSLNo6Pz4gppHU2--GQdIv2CJfwe4SU58zCh2626Ja_3dy_dY3V4fnjqbg8V1LXKFfS9bKxkSjUKnJPS9wO0apBCgyyZrQShPLfK60HIxkunrWK1sFIw4LoXW7L_-wv2aPqUPtBwZn5aMWsrZm3F9EtwvgDX_wTEN40sZvY |
| ContentType | Conference Proceeding |
| DOI | 10.5555/2492708.2493095 |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EndPage | 1596 |
| GroupedDBID | 6IE 6IF 6IK 6IL 6IN AAJGR ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK IEGSK IERZE OCL RIB RIC RIE RIL |
| ID | FETCH-LOGICAL-a227t-abb54c507747aee55fbda97d538a5001c5a37f1c7f8d354f5e8c7023c530a18b3 |
| ISBN | 3981080181 9783981080186 |
| ISICitedReferencesCount | 7 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000415126300301&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Jan 31 06:46:19 EST 2024 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | OpenURL |
| MeetingName | DATE '12: Design, Automation and Test in Europe |
| MergedId | FETCHMERGED-LOGICAL-a227t-abb54c507747aee55fbda97d538a5001c5a37f1c7f8d354f5e8c7023c530a18b3 |
| PageCount | 6 |
| ParticipantIDs | acm_books_10_5555_2492708_2493095_brief acm_books_10_5555_2492708_2493095 |
| PublicationCentury | 2000 |
| PublicationDate | 20120312 |
| PublicationDateYYYYMMDD | 2012-03-12 |
| PublicationDate_xml | – month: 03 year: 2012 text: 20120312 day: 12 |
| PublicationDecade | 2010 |
| PublicationPlace | San Jose, CA, USA |
| PublicationPlace_xml | – name: San Jose, CA, USA |
| PublicationSeriesTitle | ACM Conferences |
| PublicationTitle | Proceedings of the Conference on Design, Automation and Test in Europe |
| PublicationYear | 2012 |
| Publisher | EDA Consortium |
| Publisher_xml | – name: EDA Consortium |
| SSID | ssj0001174898 ssj0001967614 |
| Score | 1.8593441 |
| Snippet | This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and... |
| SourceID | acm |
| SourceType | Publisher |
| StartPage | 1591 |
| SubjectTerms | Applied computing -- Physical sciences and engineering -- Electronics Hardware -- Hardware validation |
| Title | Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations |
| WOSCitedRecordID | wos000415126300301&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV3Na9swFBdp2WE77aNj7T7QYLBD8RbbsSUfS9Oxy0oPGeRmZFkGQ2uH2gnd_vr9nqTYXilsOywHJxKOHL_fi9-H3gdjH6IKMgN2SVCmGQwUMVdBFmkZVEURpSZOjRCFbTYhLi_lep1dzWY_9rkwu2vRNPLuLtv8V6gxB7ApdfYf4B4WxQQ-A3QcATuO9zTiB4XP1TDZ7ff_x6w-2hpY2pgN-0zY9q3LXLRbCCsICHJ_OAf9lJfOt1ARb_DlQFNsVwfTl3r0UITipu36oKuvwVDkLalddjvUytMat6mmoZQbm-mkrZNi4_ITTncw1Sc-Q4oMql00_8C0S7Vr29LOnv1UpRn812vfJNqfSsQ1HXjr2-SGf_NqUHhIHISjDXyxPLMdS2GC1L4khbV540xSUGTo2rz4hy40snAiwDFMHxIOCV6U_7LIIjGXn_AeQ788YAdChC7xb3TOhVSUR47jLBWpbRE2_gBXvWkYp65uFF3k871LkOKjbyZqy-opOxopwUfGeMZmpnnOnkxqUb5gpQOZe5C5B5kDZD4FmXuQOYHMB5B53XCAzPcg87biHmQ-gnzEvn-5WJ1_DXwLjkBFkegDVRTJQsNmgNWpjEmSqihVJkqISWqlEepExaIKtahkGSeLKjFSC6iBOonnKpRF_JIdNm1jXjEuhNLKCCyYykWmCgWSQsIZoSEU1Dw6Zu9BpZz-SV0O05QomXtK5p6Sx-zjH8_JC3BbdfIXq71mj0fWe8MO-9utecse6V1fd7fvLEf8AoQeeMA |
| linkProvider | IEEE |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+the+Conference+on+Design%2C+Automation+and+Test+in+Europe&rft.atitle=Custom+on-chip+sensors+for+post-silicon+failing+path+isolation+in+the+presence+of+process+variations&rft.au=Li%2C+Min&rft.au=Davoodi%2C+Azadeh&rft.au=Xie%2C+Lin&rft.series=ACM+Conferences&rft.date=2012-03-12&rft.pub=EDA+Consortium&rft.isbn=3981080181&rft.spage=1591&rft.epage=1596&rft_id=info:doi/10.5555%2F2492708.2493095 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9783981080186/lc.gif&client=summon&freeimage=true |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9783981080186/mc.gif&client=summon&freeimage=true |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9783981080186/sc.gif&client=summon&freeimage=true |