Efficient Selection of Vector Instructions Using Dynamic Programming

Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scientific, and embedded applications. To take full advantage of the vector capabilities, a compiler needs to generate effici...

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Published in:2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture pp. 201 - 212
Main Authors: Barik, Rajkishore, Jisheng Zhao, Sarkar, Vivek
Format: Conference Proceeding
Language:English
Published: IEEE 01.12.2010
Subjects:
Benchmark testing
Dynamic compiler
Dynamic Optimization
Dynamic programming
Heuristic algorithms
Instruction Selection
Optimization
Registers
Tiles
Vectorization
ISBN:1424490715, 9781424490714
ISSN:1072-4451
Online Access:Get full text
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Abstract Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scientific, and embedded applications. To take full advantage of the vector capabilities, a compiler needs to generate efficient vector code automatically. However, most commercial and open-source compilers fall short of using the full potential of vector units, and only generate vector code for simple innermost loops. In this paper, we present the design and implementation of an auto-vectorization framework in the back-end of a dynamic compiler that not only generates optimized vector code but is also well integrated with the instruction scheduler and register allocator. The framework includes a novel compile-time efficient dynamic programming-based vector instruction selection algorithm for straight-line code that expands opportunities for vectorization in the following ways: (1) scalar packing explores opportunities of packing multiple scalar variables into short vectors; (2) judicious use of shuffle and horizontal vector operations, when possible; and (3) algebraic reassociation expands opportunities for vectorization by algebraic simplification. We report performance results on the impact of autovectorization on a set of standard numerical benchmarks using the Jikes RVM dynamic compilation environment. Our results show performance improvement of up to 57.71% on an Intel Xeon processor, compared to non-vectorized execution, with a modest increase in compile-time in the range from 0.87% to 9.992%. An investigation of the SIMD parallelization performed by v11.1 of the Intel Fortran Compiler (IFC) on three benchmarks shows that our system achieves speedup with vectorization in all three cases and IFC does not. Finally, a comparison of our approach with an implementation of the Superword Level Parallelization (SLP) algorithm from, shows that our approach yields a performance improvement of up to 13.78% relative to SLP.
AbstractList Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scientific, and embedded applications. To take full advantage of the vector capabilities, a compiler needs to generate efficient vector code automatically. However, most commercial and open-source compilers fall short of using the full potential of vector units, and only generate vector code for simple innermost loops. In this paper, we present the design and implementation of an auto-vectorization framework in the back-end of a dynamic compiler that not only generates optimized vector code but is also well integrated with the instruction scheduler and register allocator. The framework includes a novel compile-time efficient dynamic programming-based vector instruction selection algorithm for straight-line code that expands opportunities for vectorization in the following ways: (1) scalar packing explores opportunities of packing multiple scalar variables into short vectors; (2) judicious use of shuffle and horizontal vector operations, when possible; and (3) algebraic reassociation expands opportunities for vectorization by algebraic simplification. We report performance results on the impact of autovectorization on a set of standard numerical benchmarks using the Jikes RVM dynamic compilation environment. Our results show performance improvement of up to 57.71% on an Intel Xeon processor, compared to non-vectorized execution, with a modest increase in compile-time in the range from 0.87% to 9.992%. An investigation of the SIMD parallelization performed by v11.1 of the Intel Fortran Compiler (IFC) on three benchmarks shows that our system achieves speedup with vectorization in all three cases and IFC does not. Finally, a comparison of our approach with an implementation of the Superword Level Parallelization (SLP) algorithm from, shows that our approach yields a performance improvement of up to 13.78% relative to SLP.
Author Barik, Rajkishore
Jisheng Zhao
Sarkar, Vivek
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  givenname: Rajkishore
  surname: Barik
  fullname: Barik, Rajkishore
  email: rajkishore.barik@intel.com
  organization: Intel Corp., Santa Clara, CA, USA
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  surname: Jisheng Zhao
  fullname: Jisheng Zhao
  email: jisheng.zhao@rice.edu
  organization: Rice Univ., Houston, TX, USA
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  givenname: Vivek
  surname: Sarkar
  fullname: Sarkar, Vivek
  email: vsarkar@rice.edu
  organization: Rice Univ., Houston, TX, USA
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Snippet Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions...
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SubjectTerms Benchmark testing
Dynamic compiler
Dynamic Optimization
Dynamic programming
Heuristic algorithms
Instruction Selection
Optimization
Registers
Tiles
Vectorization
Title Efficient Selection of Vector Instructions Using Dynamic Programming
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