DRiLLS: Deep Reinforcement Learning for Logic Synthesis

Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) depends on the sequence of optimizations used. Efficient design space exploration is challenging due to the exponential number of possible optimization permutations. Therefore, automating...

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Bibliographic Details

Published in:	Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference pp. 581 - 586
Main Authors:	Hosny, Abdelrahman, Hashemi, Soheil, Shalan, Mohamed, Reda, Sherief
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.01.2020
Subjects:	Benchmark testing Circuit synthesis Delays Optimization Reinforcement learning Space exploration Tuning
ISSN:	2153-697X
Online Access:	Get full text
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