Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several othe...
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| Vydáno v: | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 617 - 624 |
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| Hlavní autoři: | , , |
| Médium: | Konferenční příspěvek Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
New York, NY, USA
ACM
1998
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| Edice: | ACM Conferences |
| Témata: | |
| ISBN: | 1581130082, 9781581130089 |
| ISSN: | 1092-3152 |
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| Abstract | This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several other objectives (e.g. minimizing maximum delay or minimizing total area subject to arrival time specifications at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee exact solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global optimal solutions. It is based on Lagrangian relaxation and `one-gate/wire-at-a-time' local optimizations, and is extremely economical and fast. For example, we can optimize a circuit with 27,648 gates and wires in about 36 minutes using under 23 MB memory on an IBM RS/6000 workstation. |
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| AbstractList | This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several other objectives (e.g. minimizing maximum delay or minimizing total area subject to arrival time specifications at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee exact solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global optimal solutions. It is based on Lagrangian relaxation and `one-gate/wire-at-a-time' local optimizations, and is extremely economical and fast. For example, we can optimize a circuit with 27,648 gates and wires in about 36 minutes using under 23 MB memory on an IBM RS/6000 workstation. |
| Author | Chen, Chung-Ping Chu, Chris C. N. Wong, D. F. |
| Author_xml | – sequence: 1 givenname: Chung-Ping surname: Chen fullname: Chen, Chung-Ping organization: Intel Corporation, 2111 N.E., 25th Ave. Hillsboro, OR and Department of Computer Sciences, University of Texas at Austin, Austin, TX – sequence: 2 givenname: Chris C. N. surname: Chu fullname: Chu, Chris C. N. organization: Department of Computer Sciences, University of Texas at Austin, Austin, TX – sequence: 3 givenname: D. F. surname: Wong fullname: Wong, D. F. organization: Department of Computer Sciences, University of Texas at Austin, Austin, TX |
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| Snippet | This paper considers simultaneous gate and wire sizing for general VLSI circuits under the Elmore delay model. We present a fast and exact algorithm which can... |
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| SubjectTerms | Applied computing -- Physical sciences and engineering -- Engineering Hardware -- Very large scale integration design Mathematics of computing -- Mathematical software |
| Title | Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation |
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