Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or Chip-Multiprocessors, provides different benefits, which has motivated process...

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Bibliographic Details
Published in:2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 481 - 492
Main Authors: Čakarević, Vladimir, Radojković, Petar, Verdú, Javier, Pajuelo, Alex, Cazorla, Francisco J., Nemirovsky, Mario, Valero, Mateo
Format: Conference Proceeding Publication
Language:English
Published: New York, NY, USA ACM 12.12.2009
IEEE
Association for Computing Machinery (ACM)
Series:ACM Conferences
Subjects:
Arquitectura de computadors
Arquitectures paral·leles
Chip scale packaging
CMP
CMT
Computer systems organization > Architectures
Computer systems organization > Dependable and fault-tolerant systems and networks
General and reference > Cross-computing tools and techniques > Performance
Hardware
Informàtica
Job Scheduling
Load management
Multithreading
Networks > Network performance evaluation
Operating systems
Performance Characterization
Process design
Processor scheduling
Resource management
Simultaneous Multithreading
Simultaneous multithreading processors
Sun
Sun Nigara T2
UltraSPARC T2
Yarn
Àrees temàtiques de la UPC
performance characterization
Sun Nigara T2
simultaneous multithreading
CMT
job scheduling
CMP
ISBN:9781605587981, 1605587982
ISSN:1072-4451
Online Access:Get full text
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Summary:Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or Chip-Multiprocessors, provides different benefits, which has motivated processor vendors to combine several TLP paradigms in each chip design. Even if most of these combined-TLP designs are homogeneous, they present different levels of hardware resource sharing, which introduces complexities on the operating system scheduling and load balancing. Commonly, processor designs provide two levels of resource sharing: Inter-core in which only the highest levels of the cache hierarchy are shared, and Intra-core in which most of the hardware resources of the core are shared. Recently, Sun Microsystems has released the UltraSPARC T2, a processor with three levels of hardware resource sharing: InterCore, IntraCore, and IntraPipe. In this work, we provide the first characterization of a three-level resource sharing processor, the UltraSPARC T2, and we show how multi-level resource sharing affects the operating system design. We further identify the most critical hardware resources in the T2 and the characteristics of applications that are not sensitive to resource sharing. Finally, we present a case study in which we run a real multithreaded network application, showing that a resource sharing aware scheduler can improve the system throughput up to 55%.
ISBN:9781605587981
1605587982
ISSN:1072-4451
DOI:10.1145/1669112.1669173