An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for accelerated execution on specialized hardware. Collapsing dataflow subgraphs will compress the latency along critical paths and reduces the number of...

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Bibliographic Details
Published in:	32nd International Symposium on Computer Architecture (ISCA'05) pp. 272 - 283
Main Authors:	Clark, Nathan, Blome, Jason, Chu, Michael, Mahlke, Scott, Biles, Stuart, Flautner, Krisztian
Format:	Conference Proceeding
Language:	English
Published:	Washington, DC, USA IEEE Computer Society 01.05.2005 IEEE
Series:	ACM Conferences
Subjects:	Acceleration Application software Application specific processors Computer architecture Computer systems organization > Architectures Computer systems organization > Architectures > Parallel architectures > Very long instruction word Computer systems organization > Architectures > Serial architectures > Complex instruction set computing Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing Computer systems organization > Embedded and cyber-physical systems Computer systems organization > Real-time systems Costs Delay General and reference > Cross-computing tools and techniques > Performance Hardware Hardware > Electronic design automation > Modeling and parameter extraction Laboratories Process design Registers
ISBN:	076952270X, 9780769522708
ISSN:	1063-6897
Online Access:	Get full text
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