Energy Efficiency Boost in the AI-Infused POWER10 Processor

We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at socket level. In addition, a new feature supportin...

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Veröffentlicht in:	Proceedings - International Symposium on Computer Architecture S. 29 - 42
Hauptverfasser:	Thompto, Brian W., Nguyen, Dung Q., Moreira, Jose E., Bertran, Ramon, Jacobson, Hans, Eickemeyer, Richard J., Rao, Rahul M., Goulet, Michael, Byers, Marcy, Gonzalez, Christopher J., Swaminathan, Karthik, Dhanwada, Nagu R., Muller, Silvia M., Wagner, Andreas, Sadasivam, Satish Kumar, Montoye, Robert K., Starke, William J., Zoellin, Christian G., Floyd, Michael S., Stuecheli, Jeffrey, Chandramoorthy, Nandhini, Wellman, John-David, Buyuktosunoglu, Alper, Pflanz, Matthias, Sinharoy, Balaram, Bose, Pradip
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.06.2021
Schlagworte:	AI acceleration Computational modeling Computer architecture Design methodology Energy efficiency microprocessor design methodology Power demand POWER10 pre-silicon modeling Sockets Technological innovation
ISSN:	2575-713X
Online-Zugang:	Volltext
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