Energy Efficiency Boost in the AI-Infused POWER10 Processor
We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at socket level. In addition, a new feature supportin...
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| Published in: | Proceedings - International Symposium on Computer Architecture pp. 29 - 42 |
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| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
01.06.2021
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| ISSN: | 2575-713X |
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| Abstract | We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at socket level. In addition, a new feature supporting inline AI acceleration was added to the POWER ISA and incorporated into the POWER10 processor core design. The resulting boost in SIMD/AI socket performance is projected to be up to 10x for FP32 and 21x for INT8 models of ResNet-50 and BERT-Large. In this paper, we describe the novel methodology deployed and used not only to obtain these efficiency boosts for traditional workloads, but also to infuse AI/ML/HPC capability directly into the POWER10 core. |
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| AbstractList | We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at socket level. In addition, a new feature supporting inline AI acceleration was added to the POWER ISA and incorporated into the POWER10 processor core design. The resulting boost in SIMD/AI socket performance is projected to be up to 10x for FP32 and 21x for INT8 models of ResNet-50 and BERT-Large. In this paper, we describe the novel methodology deployed and used not only to obtain these efficiency boosts for traditional workloads, but also to infuse AI/ML/HPC capability directly into the POWER10 core. |
| Author | Chandramoorthy, Nandhini Jacobson, Hans Byers, Marcy Stuecheli, Jeffrey Pflanz, Matthias Buyuktosunoglu, Alper Sadasivam, Satish Kumar Rao, Rahul M. Bertran, Ramon Goulet, Michael Moreira, Jose E. Wellman, John-David Thompto, Brian W. Starke, William J. Dhanwada, Nagu R. Eickemeyer, Richard J. Montoye, Robert K. Muller, Silvia M. Zoellin, Christian G. Floyd, Michael S. Gonzalez, Christopher J. Nguyen, Dung Q. Wagner, Andreas Sinharoy, Balaram Bose, Pradip Swaminathan, Karthik |
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| Snippet | We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting... |
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| SubjectTerms | AI acceleration Computational modeling Computer architecture Design methodology Energy efficiency microprocessor design methodology Power demand POWER10 pre-silicon modeling Sockets Technological innovation |
| Title | Energy Efficiency Boost in the AI-Infused POWER10 Processor |
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