On mask layout partitioning for electron projection lithography
Electron projection lithography (EPL) is a leading candidate for next generation lithography (NGL) in VLSI production. The membrane mask used in EPL is divided into sub-fields by struts for structural support. A layout must be partitioned into these sub-fields on mask and then stitched back together...
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| Vydané v: | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 514 - 518 |
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| Hlavní autori: | , , , |
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| Jazyk: | English |
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New York, NY, USA
ACM
10.11.2002
IEEE |
| Edícia: | ACM Conferences |
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| ISBN: | 0780376072, 9780780376076 |
| ISSN: | 1092-3152 |
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| Abstract | Electron projection lithography (EPL) is a leading candidate for next generation lithography (NGL) in VLSI production. The membrane mask used in EPL is divided into sub-fields by struts for structural support. A layout must be partitioned into these sub-fields on mask and then stitched back together by the EPL tool on wafer. To minimize possible stitching errors, partitioning of a mask layout should minimize cuts of layout features in the overlapping area between two adjacent sub-fields. This paper presents the first formulation of the mask layout partitioning problem for EPL as a graph problem. The graph formulation is optimally solved with a shortest path approach. Two other techniques are also presented to speed up computation. Experimental runs on data from a real industry design show excellent results. |
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| AbstractList | Electron projection lithography (EPL) is a leading candidate for next generation lithography (NGL) in VLSI production. The membrane mask used in EPL is divided into sub-fields by struts for structural support. A layout must be partitioned into these sub-fields on mask and then stitched back together by the EPL tool on wafer. To minimize possible stitching errors, partitioning of a mask layout should minimize cuts of layout features in the overlapping area between two adjacent sub-fields. This paper presents the first formulation of the mask layout partitioning problem for EPL as a graph problem. The graph formulation is optimally solved with a shortest path approach. Two other techniques are also presented to speed up computation. Experimental runs on data from a real industry design show excellent results. |
| Author | Tian, Ruiqi Yu, Ronggang Wong, D. F. Tang, Xiaoping |
| Author_xml | – sequence: 1 givenname: Ruiqi surname: Tian fullname: Tian, Ruiqi organization: Motorola Inc., Austin, TX – sequence: 2 givenname: Ronggang surname: Yu fullname: Yu, Ronggang organization: University of Texas at Austin, Austin, TX – sequence: 3 givenname: Xiaoping surname: Tang fullname: Tang, Xiaoping organization: Silicon Perspective, a Cadence Company, San Jose, CA – sequence: 4 givenname: D. F. surname: Wong fullname: Wong, D. F. organization: University of Illinois at Urbana-Champaign, Urbana, IL |
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| Keywords | Computation time Microelectronic fabrication Integrated circuit layout VLSI circuit Circuit design Partitioning Electron beam lithography Integrated circuit Shortest path Layout problem Computer aided design Wafer |
| Language | English |
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| Snippet | Electron projection lithography (EPL) is a leading candidate for next generation lithography (NGL) in VLSI production. The membrane mask used in EPL is divided... |
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| SubjectTerms | Applied sciences Computing methodologies -- Artificial intelligence -- Search methodologies Computing methodologies -- Artificial intelligence -- Search methodologies -- Discrete space search Computing methodologies -- Artificial intelligence -- Search methodologies -- Game tree search Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware -- Integrated circuits -- Semiconductor memory Hardware -- Very large scale integration design Integrated circuits Mathematics of computing -- Discrete mathematics -- Graph theory -- Paths and connectivity problems Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| Title | On mask layout partitioning for electron projection lithography |
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