The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog

With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on...

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Veröffentlicht in:	Proceedings of ACM on programming languages Jg. 7; H. OOPSLA2; S. 234 - 263
Hauptverfasser:	Chen, Qinlin, Zhang, Nairen, Wang, Jinpeng, Tan, Tian, Xu, Chang, Ma, Xiaoxing, Li, Yue
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 16.10.2023
Schlagworte:	Hardware Hardware description languages and compilation Semantics Software and its engineering Core Languages Semantics Hardware Description Languages Verilog
ISSN:	2475-1421, 2475-1421
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Abstract	With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Verilog using a core language called λV, which captures the essence of Verilog using as few language structures as possible. λV not only covers the most complete set of language features to date, but also addresses the aforementioned pitfalls. We implemented λV with about 27,000 lines of Java code, and comprehensively tested its totality and conformance with Verilog. As a reliable reference semantics, λV can detect semantic bugs in real-world Verilog simulators and expose ambiguities in Verilog’s standard specification. Moreover, as a useful core language, λV has the potential to facilitate the development of tools such as a state-space explorer and a concolic execution tool for Verilog.
AbstractList	With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Verilog using a core language called λV, which captures the essence of Verilog using as few language structures as possible. λV not only covers the most complete set of language features to date, but also addresses the aforementioned pitfalls. We implemented λV with about 27,000 lines of Java code, and comprehensively tested its totality and conformance with Verilog. As a reliable reference semantics, λV can detect semantic bugs in real-world Verilog simulators and expose ambiguities in Verilog’s standard specification. Moreover, as a useful core language, λV has the potential to facilitate the development of tools such as a state-space explorer and a concolic execution tool for Verilog. With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Verilog using a core language called λ V , which captures the essence of Verilog using as few language structures as possible. λ V not only covers the most complete set of language features to date, but also addresses the aforementioned pitfalls. We implemented λ V with about 27,000 lines of Java code, and comprehensively tested its totality and conformance with Verilog. As a reliable reference semantics, λ V can detect semantic bugs in real-world Verilog simulators and expose ambiguities in Verilog’s standard specification. Moreover, as a useful core language, λ V has the potential to facilitate the development of tools such as a state-space explorer and a concolic execution tool for Verilog.
ArticleNumber	230
Author	Zhang, Nairen Ma, Xiaoxing Tan, Tian Xu, Chang Chen, Qinlin Li, Yue Wang, Jinpeng
Author_xml	– sequence: 1 givenname: Qinlin orcidid: 0009-0006-5498-5927 surname: Chen fullname: Chen, Qinlin email: qinlinchen@smail.nju.edu.cn organization: Nanjing University, Nanjing, China – sequence: 2 givenname: Nairen orcidid: 0009-0004-3737-8768 surname: Zhang fullname: Zhang, Nairen email: nairen@smail.nju.edu.cn organization: Nanjing University, Nanjing, China – sequence: 3 givenname: Jinpeng orcidid: 0009-0007-9099-4262 surname: Wang fullname: Wang, Jinpeng email: jpwang@smail.nju.edu.cn organization: Nanjing University, Nanjing, China – sequence: 4 givenname: Tian orcidid: 0009-0009-3792-1237 surname: Tan fullname: Tan, Tian email: tiantan@nju.edu.cn organization: Nanjing University, Nanjing, China – sequence: 5 givenname: Chang orcidid: 0000-0002-6299-4704 surname: Xu fullname: Xu, Chang email: changxu@nju.edu.cn organization: Nanjing University, Nanjing, China – sequence: 6 givenname: Xiaoxing orcidid: 0000-0001-7970-1384 surname: Ma fullname: Ma, Xiaoxing email: xxm@nju.edu.cn organization: Nanjing University, Nanjing, China – sequence: 7 givenname: Yue orcidid: 0009-0009-1285-2298 surname: Li fullname: Li, Yue email: yueli@nju.edu.cn organization: Nanjing University, Nanjing, China
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SubjectTermsDisplay	Hardware -- Hardware description languages and compilation Software and its engineering -- Semantics
Title	The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog
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