Low complexity LDPC code decoders for next generation standards

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder archite...

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Published in:2007 Design, Automation & Test in Europe Conference & Exhibition : Nice, France, 16-20 April 2007 pp. 331 - 336
Main Authors: Brack, T., Alles, M., Lehnigk-Emden, T., Kienle, F., Wehn, N., L'Insalata, N. E., Rossi, F., Rovini, M., Fanucci, L.
Format: Conference Proceeding
Language:English
Published: San Jose, CA, USA EDA Consortium 16.04.2007
Series:ACM Conferences
Subjects:
Mathematics of computing
Mathematics of computing > Information theory
Mathematics of computing > Information theory > Coding theory
ISBN:3981080122, 9783981080124
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Abstract This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture.
AbstractList This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture.
Author Kienle, F.
L'Insalata, N. E.
Alles, M.
Brack, T.
Lehnigk-Emden, T.
Rossi, F.
Rovini, M.
Wehn, N.
Fanucci, L.
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  organization: University of Pisa, Pisa, Italy
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  fullname: Rovini, M.
  organization: University of Pisa, Pisa, Italy
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  givenname: L.
  surname: Fanucci
  fullname: Fanucci, L.
  organization: University of Pisa, Pisa, Italy
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Snippet This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete...
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SubjectTerms Mathematics of computing
Mathematics of computing -- Information theory
Mathematics of computing -- Information theory -- Coding theory
Title Low complexity LDPC code decoders for next generation standards
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