A New Approach to Test Generation and Test Compaction for Scan Circuits

We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select and scan-out lines are treated as conventional primary inputs or primary...

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Veröffentlicht in:Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 S. 11000
Hauptverfasser: Pomeranz, Irith, Reddy, Sudhakar M.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Washington, DC, USA IEEE Computer Society 03.03.2003
Schriftenreihe:ACM Conferences
Schlagworte:
Hardware > Communication hardware, interfaces and storage > Buses and high-speed links
Hardware > Hardware test
Hardware > Integrated circuits > Interconnect > Input > output circuits
Hardware > Robustness
ISBN:0769518702, 9780769518701
ISSN:1530-1591
Online-Zugang:Volltext
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Zusammenfassung:We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0769518702
9780769518701
ISSN:1530-1591
DOI:10.5555/789083.1022853