A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

Single-event upsets from particle strikes have become akey challenge in microprocessor design. Techniques todeal with these transient faults exist, but come at a cost.Designers clearly require accurate estimates of processorerror rates to make appropriate cost/reliability trade-offs.This paper descr...

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Vydané v:36th Annual International Symposium on Microarchitecture (MICRO-36 2003) s. 29
Hlavní autori: Mukherjee, Shubhendu S., Weaver, Christopher, Emer, Joel, Reinhardt, Steven K., Austin, Todd
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: Washington, DC, USA IEEE Computer Society 03.12.2003
Edícia:ACM Conferences
Predmet:
Hardware > Hardware validation
Hardware > Integrated circuits
Hardware > Integrated circuits > Interconnect > Input > output circuits
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
ISBN:076952043X, 9780769520438
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Abstract Single-event upsets from particle strikes have become akey challenge in microprocessor design. Techniques todeal with these transient faults exist, but come at a cost.Designers clearly require accurate estimates of processorerror rates to make appropriate cost/reliability trade-offs.This paper describes a method for generating theseestimates.A key aspect of this analysis is that some single-bit faults(such as those occurring in the branch predictor) will notproduce an error in a program's output. We define astructure's architectural vulnerability factor (AVF) as theprobability that a fault in that particular structure willresult in an error. A structure's error rate is the product ofits raw error rate, as determined by process and circuittechnology, and the AVF.Unfortunately, computing AVFs of complex structures,such as the instruction queue, can be quite involved. Weidentify numerous cases, such as prefetches, dynamicallydead code, and wrong-path instructions, in which a faultwill not affect correct execution. We instrument a detailedIA64 processor simulator to map bit-level microarchitecturalstate to these cases, generating per-structure AVFestimates. This analysis shows AVFs of 28% and 9% forthe instruction queue and execution units, respectively,averaged across dynamic sections of the entire CPU2000benchmark suite.
AbstractList Single-event upsets from particle strikes have become akey challenge in microprocessor design. Techniques todeal with these transient faults exist, but come at a cost.Designers clearly require accurate estimates of processorerror rates to make appropriate cost/reliability trade-offs.This paper describes a method for generating theseestimates.A key aspect of this analysis is that some single-bit faults(such as those occurring in the branch predictor) will notproduce an error in a program's output. We define astructure's architectural vulnerability factor (AVF) as theprobability that a fault in that particular structure willresult in an error. A structure's error rate is the product ofits raw error rate, as determined by process and circuittechnology, and the AVF.Unfortunately, computing AVFs of complex structures,such as the instruction queue, can be quite involved. Weidentify numerous cases, such as prefetches, dynamicallydead code, and wrong-path instructions, in which a faultwill not affect correct execution. We instrument a detailedIA64 processor simulator to map bit-level microarchitecturalstate to these cases, generating per-structure AVFestimates. This analysis shows AVFs of 28% and 9% forthe instruction queue and execution units, respectively,averaged across dynamic sections of the entire CPU2000benchmark suite.
Author Austin, Todd
Weaver, Christopher
Emer, Joel
Reinhardt, Steven K.
Mukherjee, Shubhendu S.
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  givenname: Shubhendu S.
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  organization: VSSAD,MMDC,Intel Corporation, 334 South Street.Shrewsbury,Massachusetts, Advanced Computer Architecture Lab, EECS Department,University of Michigan, 1301 Beal Avenue,Ann Arbor,MI
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  organization: VSSAD,MMDC,Intel Corporation, 334 South Street.Shrewsbury,Massachusetts, Advanced Computer Architecture Lab, EECS Department,University of Michigan, 1301 Beal Avenue,Ann Arbor,MI
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  givenname: Joel
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  organization: VSSAD,MMDC,Intel Corporation, 334 South Street.Shrewsbury,Massachusetts, Advanced Computer Architecture Lab, EECS Department,University of Michigan, 1301 Beal Avenue,Ann Arbor,MI
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  givenname: Steven K.
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  givenname: Todd
  surname: Austin
  fullname: Austin, Todd
  organization: Advanced Computer Architecture Lab, EECS Department,University of Michigan, 1301 Beal Avenue,Ann Arbor,MI
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SubjectTerms Hardware -- Hardware validation
Hardware -- Integrated circuits
Hardware -- Integrated circuits -- Interconnect -- Input -- output circuits
Hardware -- Very large scale integration design -- Application-specific VLSI designs -- Application specific processors
Title A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
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