A framework for scheduling multi-rate circuit simulation

This paper presents a theoretical framework for scheduling of subcircuit simulation in a multirate simulation environment. We show that event-driven simulation, selective-trace, and latency are subsumed by this framework. We assume that the circuit to be simulated is partitioned into subcircuits and...

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Vydané v:26th ACM/IEEE Design Automation Conference s. 19 - 24
Hlavní autori: Ng, A. P.-C., Visvanathan, V.
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: New York, NY, USA ACM 01.06.1989
Edícia:ACM Conferences
Predmet:
Circuit simulation
Computational modeling
Computer science
Computer simulation
Delay
Discrete event simulation
Hardware > Hardware validation > Functional verification > Simulation and emulation
Mathematics of computing > Discrete mathematics > Graph theory
Permission
Processor scheduling
Scheduling algorithm
Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis > Scheduling algorithms
Theory of computation > Design and analysis of algorithms > Online algorithms > Online learning algorithms > Scheduling algorithms
Theory of computation > Theory and algorithms for application domains > Machine learning theory > Reinforcement learning > Sequential decision making
Voltage
ISBN:0897913108, 9780897913102
ISSN:0738-100X
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Popis
Shrnutí:This paper presents a theoretical framework for scheduling of subcircuit simulation in a multirate simulation environment. We show that event-driven simulation, selective-trace, and latency are subsumed by this framework. We assume that the circuit to be simulated is partitioned into subcircuits and that the dependency relations can be expressed as a directed acyclic graph. Each subcircuit predicts its own stepsize, and we assume that a subcircuit can be simulated over some step only when all its inputs are known over that step. It is possible to show that the problem of scheduling the subcircuits subject to these constraints to minimize the amount of memory used to store intermediate voltages is NP-Complete [NV88]. We therefore propose a greedy algorithm that at each step in the schedule, simulates the subcircuit that requires the minimal amount of memory. The algorithm has been implemented in the circuit simulator XPSim, and the performance improvement due to the scheduling technique is demonstrated on a number of circuits. Extensions of the approach to cyclic dependency graphs using the method of waveform relaxation are discussed in a section on future work.
Bibliografia:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0897913108
9780897913102
ISSN:0738-100X
DOI:10.1145/74382.74387