Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm

Coarse-Grained Reconfigurable Arrays (CGRAs) balance the performance and power efficiency in computing systems. Effective compilers play a crucial role in fully realizing its potential. The compiler maps Data Flow Graphs (DFGs), which represent compute-intensive loop kernels, onto CGRAs. However, ex...

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Vydáno v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autoři: Li, Zhaoying, Wu, Dan, Wijerathne, Dhananjaya, Chen, Dan, Li, Huize, Tan, Cheng, Mitra, Tulika
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 22.06.2025
Témata:
Arrays
Design automation
Flow graphs
Kernel
Limiting
Routing
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Abstract Coarse-Grained Reconfigurable Arrays (CGRAs) balance the performance and power efficiency in computing systems. Effective compilers play a crucial role in fully realizing its potential. The compiler maps Data Flow Graphs (DFGs), which represent compute-intensive loop kernels, onto CGRAs. However, existing compilers often tackle DFG nodes individually, neglecting their intricate inter-dependencies. We introduce a novel mapping paradigm called Rewire that can place and route multiple nodes in one shot. Rewire first generates routing information that is shareable among multiple nodes via propagation. Then, Rewire intersects the routing information to generate individual placement candidates for each node. Finally, Rewire innovatively utilizes data dependencies as constraints to quickly find suitable placement for multiple nodes together. Our evaluation demonstrates that Rewire can generate more near-optimal mappings than prior works. Rewire achieves 2.1x and 1.3x performance improvement and 13.5x and 4.7x compilation time reduction, respectively, compared to two popular mappers.
AbstractList Coarse-Grained Reconfigurable Arrays (CGRAs) balance the performance and power efficiency in computing systems. Effective compilers play a crucial role in fully realizing its potential. The compiler maps Data Flow Graphs (DFGs), which represent compute-intensive loop kernels, onto CGRAs. However, existing compilers often tackle DFG nodes individually, neglecting their intricate inter-dependencies. We introduce a novel mapping paradigm called Rewire that can place and route multiple nodes in one shot. Rewire first generates routing information that is shareable among multiple nodes via propagation. Then, Rewire intersects the routing information to generate individual placement candidates for each node. Finally, Rewire innovatively utilizes data dependencies as constraints to quickly find suitable placement for multiple nodes together. Our evaluation demonstrates that Rewire can generate more near-optimal mappings than prior works. Rewire achieves 2.1x and 1.3x performance improvement and 13.5x and 4.7x compilation time reduction, respectively, compared to two popular mappers.
Author Li, Huize
Mitra, Tulika
Li, Zhaoying
Tan, Cheng
Wijerathne, Dhananjaya
Chen, Dan
Wu, Dan
Author_xml – sequence: 1
  givenname: Zhaoying
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  givenname: Dan
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  givenname: Dhananjaya
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  organization: National University of Singapore,School of Computing
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  givenname: Huize
  surname: Li
  fullname: Li, Huize
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  organization: University of Central Florida
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  givenname: Cheng
  surname: Tan
  fullname: Tan, Cheng
  email: chengtan@google.com
  organization: Google
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  givenname: Tulika
  surname: Mitra
  fullname: Mitra, Tulika
  email: huize.li@ucf.edu
  organization: National University of Singapore,School of Computing
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SubjectTerms Arrays
Design automation
Flow graphs
Kernel
Limiting
Routing
Title Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
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