Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs

To fully harness emerging computing architectures, compilers must provide intuitive input handling alongside powerful code optimization to unlock maximum performance. Coarse-Grained Reconfigurable Arrays (CGRAs) - highly energy-efficient for nested-loop applications - have lacked a compiler capable...

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Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors: Lou, Jiahang, Zhu, Qilong, Dai, Yuan, Zhong, Zewei, Yin, Wenbo, Wang, Lingli
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
Bridges
CGRA compiler
Edge computing
Energy efficiency
Hardware
loop transformation
Optimization
Pipeline processing
Program processors
Programming
Scalability
Source coding
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Summary:To fully harness emerging computing architectures, compilers must provide intuitive input handling alongside powerful code optimization to unlock maximum performance. Coarse-Grained Reconfigurable Arrays (CGRAs) - highly energy-efficient for nested-loop applications - have lacked a compiler capable of meeting these objectives. This paper introduces the Adora compiler [1], which effectively bridges user-friendly, lightweight coding inputs with high-performance acceleration on the CGRA SoC. Adora utilizes CGRA-target loop transformations to achieve efficient data-flow level execution while optimizing data communication and task pipelining at the task-flow level. Additionally, it incorporates a comprehensive automated algorithm with a thoughtfully designed optimization sequence. A series of comprehensive experiments highlights the exceptional efficiency and scalability of the Adora compiler, demonstrating its transformative impact in leveraging CGRA capabilities for acceleration in edge computing.
DOI:10.1109/DAC63849.2025.11132391