Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization

Analog IC design is mainly manual and implemented at the device level. A major reason is circuit behavior-extraction. Unlike its digital counterpart, analog IC design is strongly coupled with technology nodes and is difficult to represent by an abstract behavioral model. The lack of accurate and eff...

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Vydané v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori: Li, Jintao, Zhi, Haochang, Xiao, Jiang, Zhu, Keren, Li, Yun
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 22.06.2025
Predmet:
Accuracy
Analog circuit sizing
Analog circuits
Behavioral Model
Design automation
Integrated circuit modeling
Knowledge transfer
Kolmogorov-Arnold Networks
Life estimation
Manuals
Optimization
Testing
Transistors
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Popis
Shrnutí:Analog IC design is mainly manual and implemented at the device level. A major reason is circuit behavior-extraction. Unlike its digital counterpart, analog IC design is strongly coupled with technology nodes and is difficult to represent by an abstract behavioral model. The lack of accurate and efficient analog modeling has become a bottleneck in analog design automation. This paper proposes a behavior-centric optimization framework for analog circuits that represents circuit behavior using transistor electrical properties instead of sizes, improving model generalization and reducing optimization complexity. To characterize the process, we propose a method for mapping transistor electrical properties to sizes. Moreover, we developed a radial basis functions-based Kolmogorov-Arnold network (RBF-KAN) to accurately approximate circuit nonlinear behavior with limited simulations. Compared to blackbox modeling, our approach enables constructing surrogate models via KAN under a set specification with just a few hundred simulations. Experiments on the testing suite showed our framework achieved a 1.76 \times to 2.64 \times improvement in large signal figure of merit (FOM) and 1.73 \times to 2.48 \times in small signal FOM over state-of-the-art methods, while also enabling 3.5 \times to 6.2 \times acceleration in design porting.
DOI:10.1109/DAC63849.2025.11133189