ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly i...

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Veröffentlicht in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7
Hauptverfasser:	Li, Wenkai, Lu, Yao, Fang, Wenji, Wang, Jing, Zhang, Qijun, Xie, Zhiyao
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 22.06.2025
Schlagworte:	Accuracy Estimation Integrated circuit modeling Layout Logic gates Optimization Predictive models Registers Very large scale integration
Online-Zugang:	Volltext
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