ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly i...

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Vydáno v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autoři: Li, Wenkai, Lu, Yao, Fang, Wenji, Wang, Jing, Zhang, Qijun, Xie, Zhiyao
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 22.06.2025
Témata:
Accuracy
Estimation
Integrated circuit modeling
Layout
Logic gates
Optimization
Predictive models
Registers
Very large scale integration
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Abstract Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly impede design optimization. To address this, we propose ATLAS, which can predict the ultimate time-based layout power for any new design in the gate-level netlist. To the best of our knowledge, ATLAS is the first work that supports both time-based power simulation and general cross-design power modeling. It achieves such general timebased power modeling by proposing a new pre-training and fine-tuning paradigm customized for circuit power. Targeting golden per-cycle layout power from commercial tools, our ATLAS achieves the mean absolute percentage error (MAPE) of only {0. 5 8 \%, ~} {0. 4 5 \%}, and {5. 1 2 \%} for the clock tree, register, and combinational power groups, respectively, without any layout information. Overall, the MAPE for the total power of the entire design is \lt1 \%, and the inference speed of a workload is significantly faster than the standard flow of commercial tools.
AbstractList Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly impede design optimization. To address this, we propose ATLAS, which can predict the ultimate time-based layout power for any new design in the gate-level netlist. To the best of our knowledge, ATLAS is the first work that supports both time-based power simulation and general cross-design power modeling. It achieves such general timebased power modeling by proposing a new pre-training and fine-tuning paradigm customized for circuit power. Targeting golden per-cycle layout power from commercial tools, our ATLAS achieves the mean absolute percentage error (MAPE) of only {0. 5 8 \%, ~} {0. 4 5 \%}, and {5. 1 2 \%} for the clock tree, register, and combinational power groups, respectively, without any layout information. Overall, the MAPE for the total power of the entire design is \lt1 \%, and the inference speed of a workload is significantly faster than the standard flow of commercial tools.
Author Fang, Wenji
Xie, Zhiyao
Wang, Jing
Li, Wenkai
Lu, Yao
Zhang, Qijun
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  organization: Hong Kong University of Science and Technology
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SubjectTerms Accuracy
Estimation
Integrated circuit modeling
Layout
Logic gates
Optimization
Predictive models
Registers
Very large scale integration
Title ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
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