Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations

IC test methodologies all generate scan tests based on logical stuck-at and timing fault models that assume only a single passive physical defect localized at some circuit node. However, transistors fabricated in advanced technologies are subject to increasing random process variations that can sign...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 4
Main Authors:	Singh, Adit D., Faridi, Mukarram Ali
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Circuit Simulation Delays Digital circuits Integrated circuit modeling Integrated circuit reliability Nonlinear circuits Path Delay Testing Performance evaluation Random processes Silent Error Corruption Testing Threshold voltage Timing Failures Transistors
Online Access:	Get full text
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