Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation

This paper proposes a new design-technology cooptimization framework that expedites circuit optimization by utilizing the neural compact modeling (NCM) and a data-driven SPICE simulation. An efficient retargeting strategy of NCM and its improved design capability through a direct data driven SPICE s...

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Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Lee, Yongjeong, Lee, Seungsoo, Kim, Jeongyeol, Choi, Jungyun, Li, Zhaojie, Wu, Dehuang, Wang, Joddy
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
Data-driven SPICE model
Design-technology co-optimization
Integrated circuit modeling
Interpolation
Mathematical models
Neural compact model
Optimization
Predictive models
Robustness
Semiconductor device measurement
SPICE
Transfer learning
Transistors
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Summary:This paper proposes a new design-technology cooptimization framework that expedites circuit optimization by utilizing the neural compact modeling (NCM) and a data-driven SPICE simulation. An efficient retargeting strategy of NCM and its improved design capability through a direct data driven SPICE simulation were leveraged at the industry level in response to increasingly challenging current development situations. To facilitate rapid feedback for extensive trial and error in technology optimization, the NCM swiftly fine-tune itself using pre-trained model. Then, the data interpolation and derating techniques are utilized to provide the same design environment as before such as instance binning, process variations, and layout dependent effects. Demonstrating the robustness of our framework, we achieved a 95% reduction in PDK release time while maintaining model consistency and performance at a mid-scale design of \mathbf{1 5 k} transistors, with no SPICE run time and accuracy loss. This solution allows for rapid incorporation of process changes into the design, supporting quick path-finding during a design-technology co-development.
DOI:10.1109/DAC63849.2025.11133177