TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology

In advanced technology nodes, benefits from scaling have become limited in terms of power, performance, and area (PPA), necessitating improvements through design-technology cooptimization (DTCO). While the standard-cell methodology is widely used in modern VLSI design, it inherently constrains the p...

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Veröffentlicht in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7
Hauptverfasser:	Hsu, Chen-Hao, Pan, David Z., Perron, Laurent, Didier, Frederic, Xu, Xiaoqing, Chen, Hao
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 22.06.2025
Schlagworte:	Design methodology Layout Limiting Logic Optimization Partitioning algorithms Routing Transistors Very large scale integration
Online-Zugang:	Volltext
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