Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture

Classification tasks on ultra-lightweight devices demand devices that are resource-constrained and deliver swift responses. Binary Vector Symbolic Architecture (VSA) is a promising approach due to its minimal memory requirements and fast execution times compared to traditional machine learning (ML)...

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Vydané v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori: Duan, Shijin, Narkthong, Nuntipat, Luo, Yukui, Ren, Shaolei, Xu, Xiaolin
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 22.06.2025
Predmet:
Accuracy
Hardware acceleration
Inference algorithms
Machine learning
Machine learning algorithms
Memory management
Optimization
Performance evaluation
Power demand
Vectors
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Abstract Classification tasks on ultra-lightweight devices demand devices that are resource-constrained and deliver swift responses. Binary Vector Symbolic Architecture (VSA) is a promising approach due to its minimal memory requirements and fast execution times compared to traditional machine learning (ML) methods. Nonetheless, binary VSA's practicality is limited by its inferior inference performance and a design that prioritizes algorithmic over hardware optimization. This paper introduces UniVSA, a co-optimized binary VSA framework for both algorithm and hardware. UniVSA not only significantly enhances inference accuracy beyond current state-of-the-art binary VSA models but also reduces memory footprints. It incorporates novel, lightweight modules and design flow tailored for optimal hardware performance. Experimental results show that UniVSA surpasses traditional ML methods in terms of performance on resource-limited devices, achieving smaller memory usage, lower latency, reduced resource demand, and decreased power consumption.
AbstractList Classification tasks on ultra-lightweight devices demand devices that are resource-constrained and deliver swift responses. Binary Vector Symbolic Architecture (VSA) is a promising approach due to its minimal memory requirements and fast execution times compared to traditional machine learning (ML) methods. Nonetheless, binary VSA's practicality is limited by its inferior inference performance and a design that prioritizes algorithmic over hardware optimization. This paper introduces UniVSA, a co-optimized binary VSA framework for both algorithm and hardware. UniVSA not only significantly enhances inference accuracy beyond current state-of-the-art binary VSA models but also reduces memory footprints. It incorporates novel, lightweight modules and design flow tailored for optimal hardware performance. Experimental results show that UniVSA surpasses traditional ML methods in terms of performance on resource-limited devices, achieving smaller memory usage, lower latency, reduced resource demand, and decreased power consumption.
Author Luo, Yukui
Xu, Xiaolin
Duan, Shijin
Narkthong, Nuntipat
Ren, Shaolei
Author_xml – sequence: 1
  givenname: Shijin
  surname: Duan
  fullname: Duan, Shijin
  email: duan.s@northeastern.edu
  organization: Northeastern University
– sequence: 2
  givenname: Nuntipat
  surname: Narkthong
  fullname: Narkthong, Nuntipat
  email: narkthong.n@northeastern.edu
  organization: Northeastern University
– sequence: 3
  givenname: Yukui
  surname: Luo
  fullname: Luo, Yukui
  email: yluo11@binghamton.edu
  organization: Binghamton University
– sequence: 4
  givenname: Shaolei
  surname: Ren
  fullname: Ren, Shaolei
  email: shaolei@ucr.edu
  organization: University of California,Riverside
– sequence: 5
  givenname: Xiaolin
  surname: Xu
  fullname: Xu, Xiaolin
  email: x.xu@northeastern.edu
  organization: Northeastern University
BookMark eNo1j9FKwzAYhSPohW57A5G8QGeSP2mSy9rpJowJTr0dafp3BrZU0gzZ21tQrw58cD7OuSGXsY9IyB1nc86ZvV9UdQlG2rlgQo2Ig5CluSAzq60B4IoBk-aabFb9IQw5eLrAIewjzf23S-1AX3HoT8ljsc0pxD3GTB9CdOlMP9DnPtHt-diMXU-r5D9DHuEp4ZRcde4w4OwvJ-T96fGtXhXrl-VzXa0Lx7XNRSNKA7ZkJTBnHYJjvDO-09x5Dq300mulJDYNE22jWuOFFhJa1Slk2jMHE3L76w2IuPtK4Tgu2_3fhB8wGE1n
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/DAC63849.2025.11132468
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798331503048
EndPage 7
ExternalDocumentID 11132468
Genre orig-research
GroupedDBID 6IE
6IH
CBEJK
RIE
RIO
ID FETCH-LOGICAL-a179t-b2683960630a9ae3a01f8cf71ac13d4c4c7554ebb02db5d8c27243d5f5e07c0a3
IEDL.DBID RIE
IngestDate Wed Oct 01 07:05:15 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a179t-b2683960630a9ae3a01f8cf71ac13d4c4c7554ebb02db5d8c27243d5f5e07c0a3
PageCount 7
ParticipantIDs ieee_primary_11132468
PublicationCentury 2000
PublicationDate 2025-June-22
PublicationDateYYYYMMDD 2025-06-22
PublicationDate_xml – month: 06
  year: 2025
  text: 2025-June-22
  day: 22
PublicationDecade 2020
PublicationTitle 2025 62nd ACM/IEEE Design Automation Conference (DAC)
PublicationTitleAbbrev DAC
PublicationYear 2025
Publisher IEEE
Publisher_xml – name: IEEE
Score 2.2959232
Snippet Classification tasks on ultra-lightweight devices demand devices that are resource-constrained and deliver swift responses. Binary Vector Symbolic Architecture...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Accuracy
Hardware acceleration
Inference algorithms
Machine learning
Machine learning algorithms
Memory management
Optimization
Performance evaluation
Power demand
Vectors
Title Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
URI https://ieeexplore.ieee.org/document/11132468
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEB1s8eBJxYrf5OB1291sdpM91tbSgyyFaumtbCazIGgr7Vbw35tkt34cPHgLIRCYZJiXybw3ALdOQEWhdUAjitQ-UBQF2mgTxJQgWsSgS98lYvYg81zN59mkIat7LgwR-eIz6rqh_8s3K9y6VFnPt0UXqWpBS0pZk7Ua1m8UZr1hf2Bvk3D0E550d4t_tU3xUWN0-M_9jqDzzb9jk6_Icgx7tDyBfLx68arKbOirLljlK143bJeBD6bVuqZKsTvPsmUzn5Jn049X7eR_Wf_Hr0EHnkb3j4Nx0HRDCArrNFWgeWrBTOo0spyidlyEUamwlFGBUWwECpQWGpDWITc6MQq55CI2SZlQKDEs4lNoL1dLOgMmYmVIC0StjRBZakGecjLrVGYWT1ByDh1njMVbLXix2Nnh4o_5SzhwJncVVJxfQbtab-ka9vG9et6sb_wxfQLF1JYM
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEB20CnpSseK3OXjddjeb7GaPtbWsWJdCa-mtbJJZEGor7Vbw35ukWz8OHryFEAhMMszLZN4bgFsroCKUcUDN8sg8UAR6UkvthciVMohBFq5LxKgXZ5kYj5N-RVZ3XBhEdMVn2LBD95ev52plU2VN1xadRWIbdjhjNFjTtSreb-AnzU6rbe4TswQUyhub5b8ap7i40T34546HUP9m4JH-V2w5gi2cHUOWzqdOV5l0XN0FKV3N65JscvDeoFysyVLkzvFsycgl5cng41VaAWDS-vFvUIfn7v2wnXpVPwQvN25TepJGBs5EViXLamqHuR8UQhVxkKsg1EwxFRtwgFL6VEuuhaIxZaHmBUc_Vn4enkBtNp_hKRAWCo2SKSWlZiyJDMwTVmgdi8QgCuRnULfGmLytJS8mGzuc_zF_A3vp8Kk36T1kjxewb81v66kovYRauVjhFeyq9_Jlubh2R_YJw0uZUw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2025+62nd+ACM%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=Holistic+Design+towards+Resource-Stringent+Binary+Vector+Symbolic+Architecture&rft.au=Duan%2C+Shijin&rft.au=Narkthong%2C+Nuntipat&rft.au=Luo%2C+Yukui&rft.au=Ren%2C+Shaolei&rft.date=2025-06-22&rft.pub=IEEE&rft.spage=1&rft.epage=7&rft_id=info:doi/10.1109%2FDAC63849.2025.11132468&rft.externalDocID=11132468