Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking

Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational circuits. Recently, combinational circuit design increasingly incorporates more complex arithmetic structures, commonly known as datapath circuits...

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Veröffentlicht in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7
Hauptverfasser:	Zhou, Shuai, Zhang, Weikang, Zhang, Xindi, Jiang, Zite, You, Haihang, Cai, Shaowei
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 22.06.2025
Schlagworte:	circuit partitioning Circuits Combinational circuits Combinational Equivalence Checking Design automation Dynamic scheduling dynamic task scheduling parallel computing Parallel processing Partitioning algorithms Processor scheduling Resource management Scalability Search problems
Online-Zugang:	Volltext
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