Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational circuits. Recently, combinational circuit design increasingly incorporates more complex arithmetic structures, commonly known as datapath circuits...
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| Vydáno v: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7 |
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IEEE
22.06.2025
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| Abstract | Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational circuits. Recently, combinational circuit design increasingly incorporates more complex arithmetic structures, commonly known as datapath circuits. However, existing state-of-the-art tools often exhibit subpar performance in solving datapath CEC problems. To further advance the exploration on datapath CEC process, this study introduces PDP-CEC (Parallel Dynamic Partitioning Combinational Equivalence Checking), a novel parallel CEC approach integrating circuit partitioning and dynamic task scheduling into the CEC process, enhancing the efficiency of CEC for datapath circuits. PDP-CEC introduces an innovative method for selecting critical nodes to split the search space of the CEC problem, facilitating the efficient generation of numerous independent subproblems. Meanwhile, a dynamic task scheduling strategy is implemented in PDP-CEC to ensure load balancing and prevent hard-to-solve subproblems from stalling the entire process. Compared to the most advanced tools such as ABC and HybridCEC, PDP-CEC significantly accelerates CEC process, achieving speedups ranging from 5.11 x to 125.27 x, while effectively solving approximately three times more datapath CEC problems. With excellent scalability, PDP-CEC shows substantial improvements in combinational equivalence checking for datapath circuits, offering an efficient parallel approach to meet the demands of large-scale datapath CEC tasks. |
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| AbstractList | Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational circuits. Recently, combinational circuit design increasingly incorporates more complex arithmetic structures, commonly known as datapath circuits. However, existing state-of-the-art tools often exhibit subpar performance in solving datapath CEC problems. To further advance the exploration on datapath CEC process, this study introduces PDP-CEC (Parallel Dynamic Partitioning Combinational Equivalence Checking), a novel parallel CEC approach integrating circuit partitioning and dynamic task scheduling into the CEC process, enhancing the efficiency of CEC for datapath circuits. PDP-CEC introduces an innovative method for selecting critical nodes to split the search space of the CEC problem, facilitating the efficient generation of numerous independent subproblems. Meanwhile, a dynamic task scheduling strategy is implemented in PDP-CEC to ensure load balancing and prevent hard-to-solve subproblems from stalling the entire process. Compared to the most advanced tools such as ABC and HybridCEC, PDP-CEC significantly accelerates CEC process, achieving speedups ranging from 5.11 x to 125.27 x, while effectively solving approximately three times more datapath CEC problems. With excellent scalability, PDP-CEC shows substantial improvements in combinational equivalence checking for datapath circuits, offering an efficient parallel approach to meet the demands of large-scale datapath CEC tasks. |
| Author | Jiang, Zite Zhou, Shuai Zhang, Xindi You, Haihang Zhang, Weikang Cai, Shaowei |
| Author_xml | – sequence: 1 givenname: Shuai surname: Zhou fullname: Zhou, Shuai email: zhoushuai22s@ict.ac.cn organization: Institute of Computing Technology,Chinese Academy of Sciences,Beijing,China – sequence: 2 givenname: Weikang surname: Zhang fullname: Zhang, Weikang email: zhangweikang@ict.ac.cn organization: Institute of Computing Technology,Chinese Academy of Sciences,Beijing,China – sequence: 3 givenname: Xindi surname: Zhang fullname: Zhang, Xindi email: jiangzite19s@ict.ac.cn organization: Institute of Software, Chinese Academy of Sciences,Key Laboratory of System Software (Chinese Academy of Sciences) and State Key Laboratory of Computer Science,Beijing,China – sequence: 4 givenname: Zite surname: Jiang fullname: Jiang, Zite email: zhangxd@ios.ac.cn organization: Institute of Computing Technology,Chinese Academy of Sciences,Beijing,China – sequence: 5 givenname: Haihang surname: You fullname: You, Haihang email: caisw@ios.ac.cn organization: Institute of Computing Technology,Chinese Academy of Sciences,Beijing,China – sequence: 6 givenname: Shaowei surname: Cai fullname: Cai, Shaowei email: youhaihang@ict.ac.cn organization: Institute of Software, Chinese Academy of Sciences,Key Laboratory of System Software (Chinese Academy of Sciences) and State Key Laboratory of Computer Science,Beijing,China |
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| Snippet | Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational... |
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| SubjectTerms | circuit partitioning Circuits Combinational circuits Combinational Equivalence Checking Design automation Dynamic scheduling dynamic task scheduling parallel computing Parallel processing Partitioning algorithms Processor scheduling Resource management Scalability Search problems |
| Title | Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking |
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