Routability-aware Packing for High-density Nonvolatile FPGAs

Nonvolatile field-programmable gate arrays (NVFPGAs) can use multi-level cell (MLC) nonvolatile memories (NVMs) to enhance their logic density. However, the highdensity design of NVFPGAs degrades the intra-routability of configurable logic blocks (CLBs), which significantly prolongs the time consume...

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Bibliographic Details
Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors:	Zheng, Huichuan, Xiong, Yuqing, Zuo, Jian, Zhang, Hao, Jia, Zhenge, Zhao, Mengying
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Degradation Design automation Field programmable gate arrays Indexes Logic Logic gates Nonvolatile memory Object recognition Table lookup
Online Access:	Get full text
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Summary:	Nonvolatile field-programmable gate arrays (NVFPGAs) can use multi-level cell (MLC) nonvolatile memories (NVMs) to enhance their logic density. However, the highdensity design of NVFPGAs degrades the intra-routability of configurable logic blocks (CLBs), which significantly prolongs the time consumed by the packing process in the computer-aided design (CAD) flow. To relieve the efficiency degradation, in this paper, we propose a routability-aware re-pair stage to adjust the logical-physical look-up table (LUT) assignments to mitigate the congestion and improve their intra-routability, thereby reducing the packing time. In addition, exploiting the structural equivalence of MLC LUTs, we remove unnecessary intra-routing attempts from packing to further improve efficiency. Evaluation shows the proposed strategies reduce packing time by 41.48 \% on average. Index Terms-nonvolatile memory (NVM), multi-level cell (MLC), field-programmable gate array (FPGA), computer-aided design (CAD), packing.
DOI:	10.1109/DAC63849.2025.11133374