YAP: Yield Modeling and Simulation for Advanced Packaging

Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips and supporting multi-tier architectural designs. Cu-Cu hybrid bonding has emerged as a favored technique for the integration of chiplets a...

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Vydané v:	2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori:	Chen, Zhichao, Gupta, Puneet
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 22.06.2025
Predmet:	3D integration Accuracy Assembly Bonding chiplet Chiplets Context modeling die-to-wafer (D2W) Failure analysis hybrid bonding overlay Packaging pad recess particle defects peeling stress roughness Semiconductor device modeling Solid modeling Three-dimensional integrated circuits wafer-to-wafer (W2W) warpage/bow yield modeling
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