YAP: Yield Modeling and Simulation for Advanced Packaging
Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips and supporting multi-tier architectural designs. Cu-Cu hybrid bonding has emerged as a favored technique for the integration of chiplets a...
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| Published in: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7 |
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| Format: | Conference Proceeding |
| Language: | English |
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IEEE
22.06.2025
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| Abstract | Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips and supporting multi-tier architectural designs. Cu-Cu hybrid bonding has emerged as a favored technique for the integration of chiplets at high interconnect density. This paper introduces YAP, a yield model for wafer-to-wafer (W2W) and die-to-wafer (D2W) hybrid bonding process. The model accounts for key failure mechanisms that contribute to yield loss, including overlay errors, particle defects, Cu recess variations, excessive wafer surface roughness, and Cu density. We also develop an open-source yield simulator and compare the accuracy of the near-analytical yield model with the simulation results. The results demonstrate that YAP achieves virtually identical accuracy while offering over 10,000x faster runtime. YAP enables the co-optimization of packaging technologies, assembly design rules, and overall design methodologies. We used YAP to examine the impact of bonding pitch, compare W2W and D2W hybrid bonding for varying chiplet sizes, and explore the benefits of tighter process controls, such as improved particle defect density. |
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| AbstractList | Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips and supporting multi-tier architectural designs. Cu-Cu hybrid bonding has emerged as a favored technique for the integration of chiplets at high interconnect density. This paper introduces YAP, a yield model for wafer-to-wafer (W2W) and die-to-wafer (D2W) hybrid bonding process. The model accounts for key failure mechanisms that contribute to yield loss, including overlay errors, particle defects, Cu recess variations, excessive wafer surface roughness, and Cu density. We also develop an open-source yield simulator and compare the accuracy of the near-analytical yield model with the simulation results. The results demonstrate that YAP achieves virtually identical accuracy while offering over 10,000x faster runtime. YAP enables the co-optimization of packaging technologies, assembly design rules, and overall design methodologies. We used YAP to examine the impact of bonding pitch, compare W2W and D2W hybrid bonding for varying chiplet sizes, and explore the benefits of tighter process controls, such as improved particle defect density. |
| Author | Chen, Zhichao Gupta, Puneet |
| Author_xml | – sequence: 1 givenname: Zhichao surname: Chen fullname: Chen, Zhichao email: zhichaochen@ucla.edu organization: University of California,Department of Electrical and Computer Engineering,Los Angeles – sequence: 2 givenname: Puneet surname: Gupta fullname: Gupta, Puneet email: puneetg@ucla.edu organization: University of California,Department of Electrical and Computer Engineering,Los Angeles |
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| Snippet | Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips... |
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| SubjectTerms | 3D integration Accuracy Assembly Bonding chiplet Chiplets Context modeling die-to-wafer (D2W) Failure analysis hybrid bonding overlay Packaging pad recess particle defects peeling stress roughness Semiconductor device modeling Solid modeling Three-dimensional integrated circuits wafer-to-wafer (W2W) warpage/bow yield modeling |
| Title | YAP: Yield Modeling and Simulation for Advanced Packaging |
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